A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

A method for forming a semiconductor device includes forming a mask layer with a first implantation window on a semiconductor substrate and implanting dopants with a first implantation energy into the semiconductor substrate through the first implantation window to form a first portion of a doping region of the semiconductor device. The mask layer is adapted to form a second implantation window of the mask layer. Further, dopants are implanted with a second implantation energy into the semiconductor substrate through the second implantation window. The second implantation energy differs from the first implantation energy and a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window.

A semiconductor device includes: semiconductor layer having first and second surfaces; first base region of first conductivity type formed in the semiconductor layer; second base region of second conductivity type adjacent to the first base region and formed in the semiconductor layer; first surface region of the second conductivity type selectively formed in the first base region; second surface region of the first conductivity type selectively formed in the second base region separate from the first base region; gate electrode facing portion of the first base region between boundary between the first and second base regions and the first surface region and portion of the second base region between the boundary and the second surface region, the gate electrode extending across the boundary; first and second electrodes connected to the first and second surface regions respectively; and third electrode connected in common to the first and second base regions.

An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.

A tunnel field effect transistor includes a constant current formation layer, a source region and a drain region provided on the constant current formation layer, a channel layer provided between the source region and the drain region, a gate electrode provided on the channel layer, and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current formation layer forms a constant current between the drain region and the constant current formation layer.

A method of forming a semiconductor device includes providing a semiconductor substrate and forming amorphous semiconductor layers adjacent a major surface of the substrate. The method includes interposing dielectric layers between the amorphous semiconductor layers. The method includes forming polycrystalline semiconductor layers adjacent the amorphous semiconductor layers. The method includes interposing dielectric layers between the polycrystalline semiconductor layers and between the last amorphous semiconductor layer and the first polycrystalline semiconductor layer. The method includes forming a fine-grain polycrystalline semiconductor layer adjacent the polycrystalline semiconductor layers but is separated from the last polycrystalline semiconductor layer by an additional dielectric layer. The fine-grain polycrystalline semiconductor layer is formed at a higher temperature than the polycrystalline semiconductor layers and the amorphous semiconductor layers. A semiconductor device can be formed in another major surface of the semiconductor substrate.

An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

An electronic chip includes a doped semiconductor substrate of a first conductivity type, a doped buried layer of a second conductivity type overlying the substrate, and a first doped well of the first conductivity type overlying the buried layer. Circuit components can be formed at a top surface of the first doped well and separated from the buried layer. A current detector is coupled to the buried layer and configured detect a bias current flowing into or out of the buried layer.

The lateral bipolar junction transistor has a silicon carbide layer, the silicon carbide layer comprises a base region with a first conductivity type, a collector region with a second conductivity type and an emitter region with a second conductivity type. The collector region and the emitter region are within the base region, and the base region, collector region and emitter region are all arranged along an upper surface of the silicon carbide layer.