Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.

Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

Semiconductor element, method of reading out a quantum dot device and system. The present document relates to a semiconductor element for providing a source reservoir for a charge sensor of a quantum dot device. The element comprises a semiconductor heterostructure (2, 3, 5) including a quantum well layer (5) contiguous to a semiconductor functional layer (3), one or more ohmic contacts (9) for providing charge carriers, and a first accumulation gate electrode (13) located opposite the quantum well layer and spaced apart therefrom at least by the semiconductor functional layer for enabling to form a two dimensional charge carrier gas (14) in a first area of the quantum well layer upon applying a first biasing voltage to the first accumulation gate electrode. The device further comprises a second accumulation gate electrode (17) opposite the quantum well layer and electrically isolated from the first accumulation gate electrode (13), the second accumulation gate electrode enabling to be biased with a second biasing voltage, for enabling to extend the two dimensional charge carrier gas in a second area (18) contiguous to the first area. This document further relates to a method of determining a spin state in a quantum dot device, as well as a system comprising a quantum dot device and a semiconductor element.

Disclosed are an MPS diode device and a preparation method therefor. The MPS diode device comprises a plurality of cells arranged in parallel, wherein each cell comprises a cathode electrode, and a substrate, epitaxial layer, buffer layer, and anode electrode that are formed in succession on the cathode electrode; two active regions are formed on the side of the epitaxial layer away from the substrate; the width of forbidden band of the buffer layer is greater than the width of forbidden band of the epitaxial layer, and a material of the buffer layer and a material of the epitaxial layer are allotropes; and first openings are formed at the positions in the buffer layer opposite to the active regions, and an ohmic metal layer is formed in the first openings.

A method is provided for determining a unique identifier of a device, the device including a quantum tunnelling barrier unique to the device. The method comprises applying a potential difference across the quantum tunnelling barrier, the potential difference sufficient to enable tunnelling of charge carriers through the quantum tunnelling barrier. The method further comprises measuring an electrical signal, the electrical signal representative of a tunnelling current through the quantum tunnelling barrier, the tunnelling current characteristic of the quantum tunnelling barrier. The method further comprises determining, from the measured electrical signal, a unique identifier for the device. Related apparatuses, systems, computer-readable media and methods are also provided herein.

A method for determining an optimal spin/charge conversion operating point in a system including a pair of quantum dots including first and second quantum dots, the pair of quantum dots containing two charged particles and adopting a first charge state (2,0) in which both charged particles are in the first quantum dot, a second charge state (1,1) in which each quantum dot contains a charged particle, or a third charge state (0,2) in which both charged particles are in the second quantum dot, the charge state being a function of the voltage applied to at least two gates, the value of these voltages defining an operating point of the pair of quantum dots; the charged particles adopting a first spin state, called singlet spin state S, or a second spin state, called triplet spin state among the triplet spin state T0 or the triplet spin state T+/T−.

A quantum semiconductor device is provided. The quantum semiconductor device includes a quantum heterostructure, a dielectric layer, and an electrode. The quantum heterostructure includes a quantum well layer that includes a first 2DEG region, a second 2DEG region, and a third 2DEG region. A first tunnel barrier exists between the first 2DEG region and the second 2DEG region. A second tunnel barrier exists between the second 2DEG region and the third 2DEG region. A third tunnel barrier exists either between the first 2DEG region and the third 2DEG region. The dielectric layer is formed on the quantum heterostructure. The electrode is formed on the dielectric layer directly above the first tunnel barrier.

The disclosure describes an adaptive and optimal imaging of individual quantum emitters within a lattice or optical field of view for quantum computing. Advanced image processing techniques are described to identify individual optically active quantum bits (qubits) with an imager. Images of individual and optically-resolved quantum emitters fluorescing as a lattice are decomposed and recognized based on fluorescence. Expected spatial distributions of the quantum emitters guides the processing, which uses adaptive fitting of peak distribution functions to determine the number of quantum emitters in real time. These techniques can be used for the loading process, where atoms or ions enter the trap one-by-one, for the identification of solid-state emitters, and for internal state-detection of the quantum emitters, where each emitter can be fluorescent or dark depending on its internal state. This latter application is relevant to efficient and fast detection of optically active qubits in quantum simulations and quantum computing.

Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.