The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, including: a substrate; a first epitaxial oxide layer comprising (Ni.sub.x1Mg.sub.y1Zn.sub.1-x1-y1)(Al.sub.q1Ga.sub.1-q1).sub.2O.sub.4 wherein 0≤x1≤1, 0≤y1≤1 and 0≤q1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1-x2-y2)(Al.sub.q2Ga.sub.1-q2).sub.2O.sub.4 wherein 0≤x2≤1, 0≤y2≤1 and 0≤q2≤1. In some cases, at least one condition selected from x1≠x2, y1≠y2, and q1≠q2 is satisfied.

The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.

A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first and second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. A first conductive feature is formed over the first epitaxy region and outside an oxide diffusion region. A second conductive feature is formed over the second epitaxy region and outside the oxide diffusion region. The oxide diffusion region is disposed between the first and second conductive features.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising Li(Al.sub.x1Ga.sub.1−x1)O.sub.2 wherein 0≤x1≤1; and a second epitaxial oxide layer comprising (Al.sub.x2Ga.sub.1−x2).sub.2O.sub.3 wherein 0≤x2≤1.

Electrostatic discharge (ESD) structures are provided. An ESD structure includes a semiconductor substrate, a first epitaxy region with a first type of conductivity over the semiconductor substrate, a second epitaxy region with a second type of conductivity over the semiconductor substrate, and a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers and the second semiconductor layers are alternatingly stacked over the semiconductor substrate and between the first and second epitaxy regions. Each of the first and second semiconductor layers has a first side contacting the first epitaxy region and a second side contacting the second epitaxy region, and the first side is opposite the second side.

The present disclosure describes epitaxial oxide integrated circuits. In some embodiments, an integrated circuit comprises: a field effect transistor (FET), comprising: a substrate comprising a first oxide material; an epitaxial buried ground plane on the substrate and comprising a second oxide material; an epitaxial buried oxide layer on the epitaxial buried ground plane and comprising a third oxide material; an epitaxial semiconductor layer on the epitaxial buried oxide layer and comprising a fourth oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer and comprising a fifth oxide material with a second bandgap; electrical contacts; and a waveguide coupled to the field effect transistor. The waveguide can comprise: the epitaxial buried ground plane; the epitaxial buried oxide layer; and a signal conductor, wherein the epitaxial buried oxide layer is between the signal conductor and the epitaxial buried ground plane.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Ni.sub.x1Mg.sub.y1Zn.sub.1−x1−yl).sub.2GeO.sub.4 wherein 0≤x1≤1 and 0≤y1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1−x2−y2).sub.2GeO.sub.4 wherein 0≤x2≤1 and 0≤y2≤1. In some cases, either: x1≠x2 and y1=y2; x1=x2 and y1≠y2; or x1≠x2 and y1≠y2. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising (Mg.sub.x1Zn.sub.1−x1)(Al.sub.y1Ga.sub.1−y1).sub.2O.sub.4 wherein 0≤x1≤1 and 0≤y1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1−x2−y2).sub.2GeO.sub.4 wherein 0≤x2≤1 and 0≤y2≤1.