A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

A semiconductor device includes: a p-type region including a super-lattice pseudo mixed crystal region in which a first layer and a second layer are alternately stacked. The first layer includes a gallium oxide based semiconductor. The second layer includes a p type semiconductor made of a material different from the first layer.

Techniques, a system, and architecture are disclosed for top side transistor heat dissipation. The heat dissipation is done through single crystal epitaxially grown layer such as AlN. The architecture may include a back side heat sink to increase thermal dissipation as well. The architecture may further include a pseudomorphic channel layer that is lattice matched to the substrate.

A method for producing a semiconductor device includes a step of bonding a chip to a SOI wafer, the chip being formed of a III-V group compound semiconductor and including a substrate and a first semiconductor layer; and a step of removing the substrate and the first semiconductor layer from the chip after the step of bonding. In the producing method, the first semiconductor layer has a tensile strain, and the SOI wafer and the chip are heated to a first temperature in the step of bonding, and are cooled to a second temperature lower than the first temperature after the step of bonding.

This invention includes quantum dot channel (QDC) Si FETs, which detect infrared radiation to serve as photodetectors. GeOx-cladded Ge quantum dots form the quantum dot channel. An assembly of cladded quantum dots, such as Ge and Si, with thin barrier layers (GeOx and SiOx) form a quantum dot superlattice (QDSL). A QDSL exhibits narrow energy widths of sub-bands (or mini-energy bands) with sub-bands separation ranging ˜0.2-0.5 eV. The energy separation depends on the barrier thickness (˜0.5-1 nm) and diameter of quantum dots (3-5 nm). Drain current magnitude in a QDSL layer or quantum dot channel depends on density of electrons in the QD inversion channel, which in turn depends on number of sub-bands participating in the conduction for a given drain voltage VD and gate voltage VG. Infrared photons with energy corresponding to the intra sub-band separation are absorbed as electrons in a lower sub-band make transition to the upper sub-band.

A method for fabricating a semiconductor structure having an enhanced hole linear Rashba spin-orbit coupling effect includes: providing a substrate; and growing a germanium quantum well on the substrate. A silicon atomic layer is inserted at an interface between a well and a barrier of the germanium quantum well. The silicon atomic layer includes one or more monolayers.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.