The present disclosure belongs to the technical filed of new carbon materials and relates to a novel sp.sup.2-sp.sup.3 hybrid crystalline carbon named Gradia and its preparation process. A novel sp.sup.2-sp.sup.3 hybrid carbon named Gradia is synthesized using sp.sup.2 hybrid carbon as raw materials under high temperature and high pressure. The basic structural units of Gradia are composed of sp.sup.2 hybrid graphite-like structural units and sp.sup.3 hybrid diamond-like structural units. Gradia disclosed in the present disclosure is a class of new sp.sup.2-sp.sup.3 hybrid carbon allotrope, whose crystal structure can vary with the widths and/or crystallographic orientation relationships of internal sp.sup.2 and/or sp.sup.3 structural units.

Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

According to the present disclosure, a semiconductor manufacturing apparatus includes a rotation stage that rotates a wafer, a nozzle that supplies a chemical solution to the wafer and a nozzle movement section that moves the nozzle on a scan trajectory, wherein the nozzle movement section moves the nozzle along a first trajectory and a second trajectory on the scan trajectory, the first trajectory is a trajectory to turn around at a first turnaround point on one side and a second turnaround point on the other side with respect to a portion closest to a rotation axis of the rotation stage in the scan trajectory, and the second trajectory is a trajectory to turn around at a third turnaround point and a fourth turnaround point provided on the same side as the third turnaround point with respect to the portion closest to the rotation axis in the scan trajectory.

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 1×10.sup.−9 A/cm.sup.2 to 1×10.sup.−4 A/cm.sup.2 in a rated voltage V.sub.R.

There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

A method of addressing at least one qubit to be addressed in a set of two or more qubits includes exposing the qubit to be addressed to an electromagnetic field; and at a same time exposing another qubit of the set of two or more qubits to an electromagnetic counter field in such a way that the electromagnetic field has no effect on the other qubit or that the electromagnetic field has a different effect on the other qubit than on the qubit to be addressed. A device for performing the method includes the set of two or more qubits and electromagnetic sources for generating the electromagnetic field and electromagnetic counter field.

The present invention provides a novel semiconductor device for high breakdown voltage having no drift layer. The semiconductor device includes a first semiconductor layer of a first conductivity type which is either a p-type or an n-type conductivity type, a source portion arranged so as to be in contact with the first semiconductor layer and configured as a semiconductor portion of a second conductivity type different from the first conductivity type, a source electrode arranged in ohmic contact with the source portion, a gate electrode arranged on at least one selected from surfaces of the first semiconductor layer via a gate insulating film interposed therebetween and capable of forming by an applied electric field, an inversion layer in a region of the first semiconductor layer near the surface of the first semiconductor layer contacting the gate insulating film, a second semiconductor layer of the first conductivity type arranged so as to be in contact with the inversion layer, and a drain electrode separated from the inversion layer and arranged in Schottky contact with the second semiconductor layer.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

Provided are a diamond field effect transistor using a silicon oxide film as a gate insulating film including a silicon-terminated layer containing C—Si bonds in order to reduce an interface state density, and a method for producing the same. A FET 100A includes a silicon oxide film 3A formed on a surface of a non-doped diamond layer 2A, a non-doped diamond layer 4A formed on a surface of the non-doped diamond layer 2A using the silicon oxide film 3A as a mask, a silicon-terminated layer 5A formed at an interface between the non-doped diamond layer 2A and the silicon oxide film 3A and at an interface between the non-doped diamond layer 4A and the silicon oxide film 3A, and a gate electrode 12A formed on the silicon oxide film 3A. The FET 100A operates using the silicon oxide film 3A and an insulating film 10A formed on the silicon oxide film 3A as a gate insulating film 11A and using the non-doped diamond layer 4A as each of a source region and a drain region.