A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

The disclosed technology relates to a selector device for a memory array, and a method of forming the selector device. In some embodiments, the selector device comprises a first electrode layer embedded in an oxide; a second electrode layer arranged above the first electrode layer and separated from the first electrode layer by the oxide; and a semiconductor material forming a semiconductor layer on the top surface of the second electrode layer, and extending through the second electrode layer and the oxide onto the top surface of the first electrode layer, wherein the semiconductor material contacts the first electrode layer and the second electrode layer. In some embodiments, the selector device helps to solve the sneak path problem in the memory array it is inserted into.

A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5×10.sup.14/cm.sup.3 or more and 2×10.sup.16/cm.sup.3 or less.

A semiconductor structure, and a method for forming the same includes an amorphous semiconductor layer in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate. A hard mask memorization layer is formed directly above the amorphous semiconductor layer, portions of the amorphous semiconductor layer in contact with the top surface of the channel fin are recrystallized forming recrystallized regions. The amorphous semiconductor layer is selective removed and a second dielectric layer is deposited to form a top spacer. The hard mask memorization layer and the recrystallized regions are removed, and a first epitaxial region is formed above the channel fin followed by a second epitaxial region positioned above the first epitaxial region and between the second dielectric layer forming a top source/drain of the semiconductor structure.

A semiconductor device includes a substrate; and a fin protruding from the substrate. The fin includes a first material and a second material. The fin includes a lower section, a middle section, and an upper section. The middle section has a smaller width at a middle portion than a width at lower and upper portions of the middle section. A concentration of the second material gradually decreases from the middle portion in upward and downward directions.

A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

A method of manufacturing a semiconductor device includes: forming one or more transistor cells in a first region of a semiconductor substrate, the semiconductor substrate having a second region that is devoid of transistor cells; forming a first dielectric material over the first and second regions; forming a second dielectric material over the first dielectric material; forming a pn diode in the first dielectric material over the second region; etching first contact grooves into a p-type region of the pn diode, second contact grooves into an n-type region of the pn diode, and third contact grooves into the first region of the semiconductor substrate at the same time using a common contact formation process; and filling the first contact grooves, the second contact grooves and the third contact grooves with an electrically conductive material.

Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.