A signal transmission device relating to a technique disclosed in the specification of the present application includes: an isolation transformer; an input-side circuit connected to an input side of the isolation transformer; and an output-side circuit connected to an output side of the isolation transformer. The output-side circuit includes a first differential circuit having a first input and a second input connected to the first terminal and the second terminal respectively. A reference potential of the first differential circuit is connected to the second terminal.

A Schottky barrier diode according to an exemplary embodiment of the present disclosure includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n− type layer and separated from each other; an anode disposed on the n− type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate, wherein the p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n− type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

A semiconductor device includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench formed in the n− type layer and separated from each other; an n+ type region disposed between a side surface of the first trench and the side surface of the second trench and disposed on the n− type layer; a gate insulating layer disposed inside the first trench; a source insulating layer disposed inside the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer, the n+ type region, and the source insulating layer; and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate.

According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.

A laser irradiation method of irradiating, with a pulse laser beam, an irradiation object in which an impurity source film is formed on a semiconductor substrate includes: reading fluence per pulse of the pulse laser beam with which a rectangular irradiation region set on the irradiation object is irradiated and the number of irradiation pulses the irradiation region is irradiated, the fluence being equal to or larger than a threshold at or beyond which ablation potentially occurs to the impurity source film when the irradiation object is irradiated with pulses of the pulse laser beam in the irradiation pulse number and smaller than a threshold at or beyond which damage potentially occurs to the surface of the semiconductor substrate; calculating a scanning speed Vdx; and moving the irradiation object at the scanning speed Vdx relative to the irradiation region while irradiating the irradiation region with the pulse laser beam at the repetition frequency f.

A semiconductor device includes a JFET and a MOSFET cascode-connected to each other such that a source electrode of the JFET is connected to a drain electrode of the MOSFET. The JFET is configured such that a breakdown voltage between a gate layer and a body layer is set lower than a breakdown voltage of the MOSFET.

A silicon carbide crystal includes a seed layer, a bulk layer, and a stress buffering structure formed between the seed layer and the bulk layer. The seed layer, the bulk layer, and the stress buffering structure are each formed with a dopant that cycles between high and low dopant concentration. The stress buffering structure includes a plurality of stacked buffer layers and a transition layer over the buffer layers. The buffer layer closest to the seed layer has the same variation trend of the dopant concentration as the buffer layer closest to the transition layer, and the dopant concentration of the transition layer is equal to the dopant concentration of the seed layer.

A method for forming an electrical contact is provided. The method includes grinding a silicon carbide surface using a grinding disk which includes a grinding face containing nickel or a nickel compound, such that particles of the nickel or nickel compound from the grinding disk are embedded in the ground silicon carbide surface, and hardening the ground silicon carbide surface with the aid of a laser, such that at least some of the embedded nickel particles form a nickel silicide with silicon from the silicon carbide.

A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.

A method of splitting off a semiconductor wafer from a semiconductor bottle includes: forming a separation region within the semiconductor boule, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor boule; and applying an external force to the semiconductor boule such that at least one crack propagates along the separation region and a wafer splits from the semiconductor boule.