Doped nitride-based semiconductor materials and methods of producing these materials are described herein.

Doped nitride-based semiconductor materials and methods of producing these materials are described herein.

Embodiments of the present application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a first doped nitride semiconductor layer disposed on the semiconductor layer, and a second doped nitride semiconductor layer disposed on the first doped nitride semiconductor layer. The semiconductor device further includes an undoped nitride semiconductor layer between the semiconductor layer and the first doped nitride semiconductor layer. The undoped nitride semiconductor layer has a first surface in contact with the semiconductor layer and a second surface in contact with the first doped nitride semiconductor layer.

Embodiments of the present application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a first doped nitride semiconductor layer disposed on the semiconductor layer, and a second doped nitride semiconductor layer disposed on the first doped nitride semiconductor layer. The semiconductor device further includes an undoped nitride semiconductor layer between the semiconductor layer and the first doped nitride semiconductor layer. The undoped nitride semiconductor layer has a first surface in contact with the semiconductor layer and a second surface in contact with the first doped nitride semiconductor layer.

An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.