Patent classifications
H01L29/2203
GaN LAMINATE AND METHOD OF MANUFACTURING THE SAME
To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.
SULFUR-CONTAINING THIN FILMS
In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
Light-activated compositions and methods using the same
The invention includes light-activated compositions and methods that are useful for promoting cell death or growth. In certain embodiments, the compositions comprise quantum dots (QD).
Compositionally matched molecular solders for semiconductors
Chalcogenidometallates of group IIB, IV and V elements and, particularly, alkali metal-containing chalcogenidometallates of cadmium, lead and bismuth are provided. Also provided are methods of using the chalcogenidometallates as molecular solders to form metal chalcogenide structures, including thin films, molded objects and bonded surfaces composed of metal chalcogenides.
Surface doping of nanostructures
This disclosure provides systems, methods, and apparatus related to surface doping of nanostructures. In one aspect a plurality of nanostructures is fabricated with a solution-based process using a solvent. The plurality of nanostructures comprises a semiconductor. Each of the plurality of nanostructures has a surface with capping species attached to the surface. The plurality of nanostructures is mixed in the solvent with a dopant compound that includes doping species. During the mixing the capping species on the surfaces of the plurality of nanostructures are replaced by the doping species. Charge carriers are transferred between the doping species and the plurality of nanostructures.
Sulfur-containing thin films
In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
Methods for the preparation of colloidal nanocrystal dispersion
Methods of preparing a dispersion of colloidal nanocrystals (NCs) for use as NC thin films are disclosed. A dispersion of NCs capped with ligands may be mixed with a solution containing chalcogenocyanate (xCN)-based ligands. The mixture may be separated into a supernatant and a flocculate. The flocculate may be dispersed with a solvent to form a subsequent dispersion of NCs capped with xCN-based ligands.
Methods of forming colloidal nanocrystal-based thin film devices
Methods of forming colloidal nanocrystal (NC)-based thin film devicesare disclosed. The methods include the steps of depositing a dispersion of NCs on a substrate to form a NC thin-film, wherein at least a portion of the NCs is capped with chalcogenocyanate (xCN)-based ligands; and doping the NC thin-film with a metal.
Bidirectional JFET and a process of forming the same
An electronic device comprising a bidirectional JFET can include a drain/source region; a lightly doped semiconductor layer overlying the drain/source region; a source/drain region overlying the lightly doped semiconductor layer; a trench extending through the source/drain region and into the lightly doped semiconductor layer; a gate electrode of the bidirectional JFET within the trench; and a field electrode within the trench. A process of forming an electronic device can include providing a workpiece including a first doped region and a lightly doped semiconductor layer overlying the first doped region; defining a trench extending into the lightly doped semiconductor layer; forming a gate electrode within the trench, wherein the gate electrode extends to a sidewall of the trench; and forming a field electrode within the trench, wherein a bidirectional JFET includes the first doped region, the lightly doped semiconductor layer, a second doped region, and the gate electrode.
Method of manufacturing a semiconductor device having a vertical edge termination structure
A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.