The embodiments of the present invention provides an oxide TFT, an array substrate and a display device, an oxide channel layer of the oxide TFT comprises a front channel oxide layer and a back channel oxide layer, a conduction band bottom of the back channel oxide layer being higher than a conduction band bottom of the front channel oxide layer, and a band gap of the back channel oxide layer being larger than a band gap of the front channel oxide layer. In the oxide TFT, the array substrate and the display device provided in the present invention, it is possible to accumulate a large number of electrons through the potential difference formed between oxide channel layers of a multilayer structure so as to increase the carrier concentration in the oxide channel layers to achieve the purpose of improving TFT mobility without damaging TFT stability.

The embodiments of the present invention provides an oxide TFT, an array substrate and a display device, an oxide channel layer of the oxide TFT comprises a front channel oxide layer and a back channel oxide layer, a conduction band bottom of the back channel oxide layer being higher than a conduction band bottom of the front channel oxide layer, and a band gap of the back channel oxide layer being larger than a band gap of the front channel oxide layer. In the oxide TFT, the array substrate and the display device provided in the present invention, it is possible to accumulate a large number of electrons through the potential difference formed between oxide channel layers of a multilayer structure so as to increase the carrier concentration in the oxide channel layers to achieve the purpose of improving TFT mobility without damaging TFT stability.

A light-emitting element includes an n-type semiconductor layer mainly including Al.sub.xGa.sub.1XN (0.5x1), a p-type semiconductor layer, a light-emitting layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer, an n-electrode connected to the n-type semiconductor layer, and a plurality of p-electrodes that are connected to the p-type semiconductor layer and are arranged in a dot pattern. An area of the n-electrode is not less than 25% and not more than 50% of a chip area.

Various embodiments of a semiconductor device and related fabrication methods are disclosed. In one exemplary embodiment, the semiconductor device may include a substrate and a plurality of two-dimensional semiconductor films over the substrate, where a photogain of the two-dimensional films is above about 10.sup.3 when measured at room temperature. In another exemplary embodiment, a semiconductor device may comprise a substrate comprising nanorods or nanodots and a plurality of two-dimensional films disposed on the substrate.

Various embodiments of a semiconductor device and related fabrication methods are disclosed. In one exemplary embodiment, the semiconductor device may include a substrate and a plurality of two-dimensional semiconductor films over the substrate, where a photogain of the two-dimensional films is above about 10.sup.3 when measured at room temperature. In another exemplary embodiment, a semiconductor device may comprise a substrate comprising nanorods or nanodots and a plurality of two-dimensional films disposed on the substrate.

This application relates to an active switch array substrate, a manufacturing method therefor, and a display panel using same. The active switch array substrate includes: a substrate; a gate electrode, configured on the substrate; an insulation protection layer, configured on the gate electrode; a semiconductor active layer, configured on the gate electrode and the insulation protection layer; an active layer channel, formed on a dent surface layer above the middle of the semiconductor active layer; a source electrode, configured at one side of the semiconductor active layer and forming ohmic contact with the semiconductor active layer; a drain electrode, configured at the other side of the semiconductor active layer and forming ohmic contact with the semiconductor active layer; and a passivation layer, covering the semiconductor active layer, the source electrode, and the drain electrode.

This application relates to an active switch array substrate, a manufacturing method therefor, and a display panel using same. The active switch array substrate includes: a substrate; a gate electrode, configured on the substrate; an insulation protection layer, configured on the gate electrode; a semiconductor active layer, configured on the gate electrode and the insulation protection layer; an active layer channel, formed on a dent surface layer above the middle of the semiconductor active layer; a source electrode, configured at one side of the semiconductor active layer and forming ohmic contact with the semiconductor active layer; a drain electrode, configured at the other side of the semiconductor active layer and forming ohmic contact with the semiconductor active layer; and a passivation layer, covering the semiconductor active layer, the source electrode, and the drain electrode.

The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.

The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.

A HEMT made of nitride semiconductor materials and a process of forming the same are disclosed, where the HEMT has n-type regions beneath the source and drain electrodes with remarkably increased carrier concentration. The HEMT provides the n-type regions made of at least one of epitaxially grown ZnO layer and MgZnO layer each doped with at least aluminum and gallium with density higher than 110.sup.20 cm.sup.3. The process of forming the HEMT includes steps of forming recesses by dry-etching, epitaxially growing n-type layer, removing surplus n-type layer except within the recesses by dry-etching using hydrocarbon, and forming the electrodes on the n-type layer.