A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

A location displacement of an electrode of a device relative to an electrode pad of a semiconductor element is detected based on a conduction state between the electrode pad of the semiconductor element and the electrode of the device. The electrode pad of the semiconductor element is segmented into multiple portions and a first pad through a fourth pad uniformly arranged. A location displacement detector determines that no location displacement has occurred when the electrode pad of the semiconductor element is conductive to the electrode of the device, and determines that a location displacement has occurred when the electrode pad of the semiconductor element is non-conductive to the electrode of the device.

An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

Provided is a semiconductor light emitting device including nodes each connected to a gate of a shift thyristor and a gate of a light emitting thyristor and transfer diodes arranged to connect the nodes to each other. The shift thyristor has a laminated structure including semiconductor layers, and is provided to a mesa formed separately from the light emitting thyristors and the transfer diodes. The shift thyristor includes a first metal layer continuously provided to straddle the mesa, and a second metal layer, which is arranged in an upper layer than the first metal layer, and includes a first part and a second part arranged to be opposed to the first part across the mesa. The first part and the second part of the second metal layer are each electrically connected to the first metal layer in a region that does not overlap the mesa in a plan view.

A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second complementary conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode, and the front-side base region is electrically connected to a front-side electrode. A turn-on structure, which is an emitter structure of the second conduction type, is embedded into the front-side base region and/or rear-side base region and is covered by the respective electrode and is electrically contacted with the electrode placed on the base region respectively embedding it. It can be turned on by a trigger structure which can be activated by an electrical turn-on signal. In the activated state, the trigger structure injects an electrical current surge into the semiconductor body, which irreversibly destroys a semiconductor junction.

A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

To form p-type semiconductor regions in a gallium nitride (GaN)-based semiconductor by ion implantation. A method for manufacturing a semiconductor device comprises forming first grooves, depositing, and ion-implanting. At the step of forming the first grooves, the first grooves are formed in a stacked body including a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first grooves each have a bottom portion located in the first semiconductor layer. At the depositing step, the p-type impurity is deposited on side portions and the bottom portions of the first grooves. At the ion-implanting step, the p-type impurity is ion-implanted into the first semiconductor layer through the first grooves.