A display device, includes: a pixel connected to a scan line and a data line crossing the scan line, wherein the pixel includes a light emitting element, a driving transistor configured to control a driving current supplied to the light emitting element according to a data voltage received from the data line, and a first switching transistor configured to apply the data voltage of the data line to the driving transistor according to a scan signal applied to the scan line; wherein the driving transistor includes a first active layer including an oxide semiconductor and a first oxide layer on the first active layer and including an oxide semiconductor; and wherein the first switching transistor includes a second active layer on the first active layer and including the same oxide semiconductor as the first oxide layer.

What is provided is a transistor including a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, in which the gate insulating film is a laminated film in which a SiO.sub.x film and a SiC.sub.yN.sub.z film are alternately formed, the total number of films constituting the laminated film is 3 or more and 18 or less, and the thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less.

In some embodiments of the present disclosure, a method for forming a semiconductor device is described. A semiconductor layer is formed and a dielectric layer is formed. A pressurized treatment is performed to transform the semiconductor layer into a low-doping semiconductor layer and transform the dielectric layer into a crystalline ferroelectric layer. A gate layer is formed. An insulating layer is formed over the gate layer, the crystalline ferroelectric layer and the low-doping semiconductor layer. Contact openings are formed in the insulating layer exposing portions of the low-doping semiconductor layer. Source and drain terminals are formed on the low-doping semiconductor layer.

Provided are methods of manufacturing comprising providing a FET base structure, the FET base structure comprising a substrate, a drain and a source; and providing a channel layer on the FET base structure; and providing a first layer on the FET base structure. The first layer comprises a one-dimensional or two-dimensional material and is arranged on an upper surface of the channel layer so as to form a sensing surface of the FET. The step of providing the channel layer comprises forming the channel layer and subsequently transferring the channel layer onto the FET base structure. Alternatively or additionally, the step of providing the first layer on the FET base structure comprises forming the first layer and subsequently transferring the first layer onto the FET base structure.

One example provides an integrated circuit comprising a transistor including a semiconductor channel. The semiconductor channel includes three or more sub-channels, one or more nodes, each node being a junction of at least three sub-channels, and channel ends. A Schottky contact at each channel end forms a source or drain contact, and a gate contact disposed at each Schottky contact controls a barrier conductivity of the corresponding Schottky contact.

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a semiconducting metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The semiconducting metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

A semiconductor device includes a substrate, an oxide semiconductor layer over the substrate, a gate insulating layer over the oxide semiconductor layer, a metal oxide layer over the gate insulating layer, and a gate electrode over the metal oxide layer. A first side surface of the metal oxide protrudes from a second side surface of the gate electrode in a plan view.

A thin film transistor substrate can include a buffer layer on a base substrate and having a first buffer layer and a second buffer layer; a semiconductor layer disposed on the buffer layer; a gate insulating film on the semiconductor layer; and a gate electrode spaced apart from the semiconductor layer, at least a part of the gate electrode overlapping with the semiconductor layer. The base substrate, the first buffer layer, the second buffer layer, the semiconductor layer, the gate insulating film and the gate electrode are sequentially stacked, and a surface oxygen concentration of the first buffer layer is higher than a surface oxygen concentration of the second buffer layer.

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

A display device may include a first gate electrode disposed on a substrate, a buffer layer disposed on the first gate electrode, a first active pattern on the buffer layer, the first active pattern overlapping the first gate electrode and including an oxide semiconductor, a second active pattern on the buffer layer, spaced apart from the first active pattern, and including an oxide semiconductor, the second active pattern including a channel region, and a source region and a drain region, a source pattern and a drain pattern respectively at ends of the first active pattern, a first insulation pattern disposed on the first active pattern, a second insulation pattern disposed on the channel region, a first oxygen supply pattern on the first insulation pattern, a second oxygen supply pattern on the second insulation pattern, and a second gate electrode on the second oxygen supply pattern.