A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.

A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.

An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

A field effect transistor (FET) includes a gate dielectric layer, a two-dimensional (2D) channel layer formed on the gate dielectric layer and a gate electrode. The 2D channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET. The 2D channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region. A source electrode covers the first finger regions, and a drain electrode covers the second finger regions.

According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of 10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

A method for use in manufacturing an electronic component comprises forming a layered structure comprising a dielectric structure layer, a channel layer and a gate layer. The dielectric structure layer comprises a first portion and a second portion that differ from one another in respect of fixed charges. The channel layer comprises a two-dimensional material. The gate layer comprises a gate formed above both, the first portion of the dielectric structure layer and the second portion of the dielectric structure layer. A device for use as an electronic component comprises a dielectric structure and a gate above the dielectric structure and a two-dimensional material between the dielectric structure and the gate. The dielectric structure is configured to expose the two-dimensional material to an inhomogeneous electric field.

A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.

There is provided a method for planarizing irregularities in a surface of a grapheme layer formed on a substrate, including: planarizing the grapheme layer by removing graphene constituting a convex portion in the surface of the grapheme layer by anisotropically etching the grapheme layer using a plasma etching in an in-plane direction from an edge portion of the graphene.

New compositions of matter and device constructs are disclosed in the form of diamond material layers or films having one or more surfaces treated with chemically active radicals, e.g., photo-radical or thermal-radical generators to reduce and stabilize their surface resistance. The compositions exhibit stable, markedly lower surface resistances, e.g., below about 3 k sq.sup.1 or between about 3 and 2 k sq.sup.1 or below 2 k sq.sup.1, or below 1 k sq.sup.1, or lower. In certain embodiments, the diamond material is a epitaxial layer grown on a substrate, e.g., by microwave plasma chemical vapor deposition (CVD) and can have a thickness ranging from about 1 nm to 1 mm, preferably from about 10 nm to 500 m, or from about 100 nm to 10 m. The invention also encompasses semiconductor devices fabricated from the surface-modified diamond materials disclosed herein. For example, device can be a field effect transistor in which the diamond material provides a hole conductivity channel between a source region and a drain region that is activated by a voltage applied to an intermediate gate region. Methods are also disclosed for modifying diamond surfaces to decrease and stabilize their surface resistance.