A semiconductor device includes a semiconductor layer including a super junction layer in which an n-type pillar layer and a p-type pillar layer are alternately disposed and a p-type withstand voltage holding structure formed on an upper layer part of the semiconductor layer to surround an active region. At least one withstand voltage holding structure overlaps with the super junction layer in a plan view. At least one withstand voltage holding structure overlapping with the super junction layer in a plan view has a gap which is an intermittent part of the withstand voltage holding structure.

The present invention relates to a semiconductor device, wherein the semiconductor substrate includes: a semiconductor layer; and a well region, the semiconductor device includes: a surface electrode provided on a second main surface on a side opposite to a first main surface; a back surface electrode provided on the first main surface; and an upper surface film covering an end edge portion of the surface electrode and at least part of an outer side region outside an end surface of the surface electrode of the semiconductor substrate, the well region includes a portion extending to the outer side region and a portion extending to an inner side region inside the end surface of the surface electrode, and the upper surface film includes at least one outer peripheral opening part provided along an outer periphery of the surface electrode away from the surface electrode of the outer side region.

An SBD of a JBS structure has on a front side of a semiconductor substrate, nickel silicide films in ohmic contact with p-type regions and a FLR, and a titanium film forming a Schottky junction with an n.sup.−-type drift region. A thickness of each of the nickel silicide films is in a range from 300 nm to 700 nm. The nickel silicide films each has a first portion protruding from the front surface of the semiconductor substrate in a direction away from the front surface of the semiconductor substrate, and a second portion protruding in the semiconductor substrate from the front surface of the semiconductor substrate in a depth direction. A thickness of the first portion is equal to a thickness of the second portion. A width of the second portion is wider than a width of the first portion.

A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.

A semiconductor device includes: a drift layer of a first conductivity type which is made of silicon carbide; a junction region formed on one main surface of the drift layer; a junction termination extended region of the drift layer, the junction termination extended region being formed outside the junction region when the one main surface is viewed in plan view, and the junction termination extended region containing an impurity of a second conductivity type opposite to the first conductivity type; and a guard ring region of the drift layer, the guard ring region being formed at a position overlapping the junction termination extended region when the one main surface is viewed in plan view, and the guard ring region containing the impurity of the second conductivity type with a concentration that is higher than that of the junction termination extended region, wherein in the junction termination extended region, the concentration of the impurity of the second conductivity type in a depth direction from the one main surface increases from the one main surface down to a first depth, and the concentration of the impurity of the second conductivity type at the one main surface is one tenth or less the concentration of the impurity of the second conductivity type at the first depth and is higher than a concentration of an impurity of the first conductivity type of the drift layer.

In this semiconductor device, a trench is formed on the upper surface of an n-type semiconductor layer laminated on a semiconductor substrate, a Schottky junction with metal is formed on the upper surface of an n-type region forming one side surface of the trench, and a pn junction is formed on the upper surface of an n-type region forming the other side surface of the trench. The pn junction is formed by a junction between the n-type region and the p-type semiconductor layer crystal-grown via epitaxial growth on the upper surface of the n-type region forming the other side surface.

A silicon carbide diode having a high surge current capability, and including a semiconductor base plate. The semiconductor base plate includes an N-type silicon carbide substrate and an N-type silicon carbide epitaxial layer located on the N-type silicon carbide substrate. The upper portion of the N-type silicon carbide epitaxial layer is provided with a plurality of P-type well regions. The N-type high resistance region is provided under the P-type well region or on the lower surface of the P-type well region. The resistivity of the N-type high resistance region is greater than the resistivity of the N-type silicon carbide epitaxial layer. The N-type high resistance region is provided under the P-type well region, and a plurality of grooves are provided in the P-type well region or a plurality of block-shaped P-type regions uniformly arranged at intervals are provided in the N-type high resistance region.

A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10.

A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type thereon; a second semiconductor layer of a second conductivity type deposited using epitaxial growth on a bottom of the first semiconductor layer; a trench including a lateral surface constituted by the first semiconductor layer and a bottom surface at least partly constituted by the second semiconductor layer; an insulating film that covers the bottom surface and the lateral surface; a conductive body inside the trench; and a metal film electrically connected to the conductive body and forms a Schottky barrier with a surface of the first semiconductor layer. The second semiconductor layer constitutes all or a middle portion of the bottom surface and is within the trench in a plan view of the substrate.

A grid is manufactured with a combination of ion implant and epitaxy growth. The grid structure is made in a SiC semiconductor material with the steps of a) providing a substrate comprising a doped semiconductor SiC material, said substrate comprising a first layer (n1), b) by epitaxial growth adding at least one doped semiconductor SiC material to form separated second regions (p2) on the first layer (n1), if necessary with aid of removing parts of the added semiconductor material to form separated second regions (p2) on the first layer (n1), and c) by ion implantation at least once at a stage selected from the group consisting of directly after step a), and directly after step b); implanting ions in the first layer (n1) to form first regions (p1). It is possible to manufacture a grid with rounded corners as well as an upper part with a high doping level. It is possible to manufacture a component with efficient voltage blocking, high current conduction, low total resistance, high surge current capability, and fast switching.