A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.

Disclosed is a cellular structure of a silicon carbide MOSFET device, and a silicon carbide MOSFET device. The cellular structure comprises: second conductive well regions located on two sides of the cellular structure and arranged within the surface of a drift layer, first conductive source regions located within the surfaces of the well regions, and a gate structure located at the center of the cellular structure and in contact with the source regions, the well regions, and the drift layer. The cellular structure further comprises a source metal layer located above the source regions and forming ohmic contact with the source regions; on two sides of the cellular structure, side trenches are formed downwardly on regions of the drift layer that are not covered by the well regions; Schottky metal layers forming Schottky contact with the drift layer below the side trenches are arranged in the side trenches.

A silicon carbide semiconductor device includes: a body region of a second conductivity type provided on a drift layer of a first conductivity type; a source region of a first conductivity type provided on the body region; a source electrode connected to the source region; a gate insulating film provided on an inner surface of a trench; a gate electrode provided inside the trench with interposition of the gate insulating film; a protective layer of a second conductivity type provided below the gate insulating film; a connection layer of a second conductivity type being in contact with the protective layer and the body region; and an electric field relaxation layer of a second conductivity type being in contact with a bottom surface of the connection layer, provided below the connection layer, and having a lower impurity concentration of a second conductivity type than the connection layer.

The present disclosure can be applied to semiconductor devices and, in particular, relates to a MOSFET device made of silicon carbide and a method for manufacturing same. A metal-oxide film semiconductor field-effect transistor device of the present disclosure may comprise: a drain electrode; a substrate arranged on the drain electrode; an N-type drift layer arranged on the substrate; a current-spreading layer arranged on the drift layer; P-type well layers arranged on the current-spreading layer to define a channel; an N+ region arranged on the well layers; a damage prevention layer adjacent to the N+ region and having a lower N-type doping concentration than that of the N+ region; a P+ region arranged on one side of the channel; a gate oxide layer arranged on the current-spreading layer; a gate layer arranged on the gate oxide layer; and a source electrode arranged on the gate layer.

A silicon carbide semiconductor device includes a substrate, a drift layer, a base layer, a first electrode, and a second electrode. The substrate includes a cell region at which a semiconductor element is disposed and a temperature detection region at which a diode element is disposed. The first electrode is disposed at a side facing the substrate with the drift layer sandwiched between the substrate and the first electrode. The second electrode is disposed at a side facing the drift layer with the substrate sandwiched between the drift layer and the second electrode. The semiconductor element includes a first impurity region and a second impurity region disposed at a surface layer portion of the base layer. The diode element includes a first constituent layer at a surface layer portion of the base layer and a second constituent layer connected to the first constituent layer.

A bottom of a trench is an Si plane or a C plane while sidewalls of the trench are an m-plane. In the trench, a gate electrode is provided via a gate insulating film. The gate insulating film is a HTO film with a thickness of at least 50 nm. By a post-HTO-deposition annealing at a temperature in a range of 1250 degrees C. to 1300 degrees C. under a mixed gas atmosphere containing nitric oxide, nitrogen, and oxygen, the film density of the gate insulating film is within a range of 2.21 g/cm.sup.3 to 2.38 g/cm.sup.3. The total oxygen flow amount of the mixed gas atmosphere of the post-HTO-deposition annealing is at most 5%. The gate insulating film has a two-layer structure including a low-density film that is within 3 nm from a SiC/SiO.sub.2 interface and has a relatively low film density, and a high- density film that is at least 3 nm apart from the SiC/SiO.sub.2 interface and has a relatively high film density.

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×10.sup.14 cm.sup.−3 and less than or equal to 5×10.sup.16 cm.sup.−3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms.

A method forms a part of a power semiconductor device. The method includes homoepitaxially forming two silicon carbide layers on a first side of a silicon carbide substrate and forming a pattern of pits on a second side of the silicon carbide substrate. The two layers include a buffer layer, on the first side of the silicon carbide substrate, and have a same doping type of the silicon carbide substrate and a doping concentration equal to or greater than 10.sup.17 cm.sup.−3 in order to increase the quality of at least one subsequent SiC layer. The two layers include an etch stopper layer, being deposited on the buffer layer and has a same doping type as the buffer layer but a lower doping concentration in order to block a trenching process. The pattern of pits, obtained by electrochemical etching, extends completely thorough the silicon carbide substrate and the buffer layer.

P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 μm. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 3×10.sup.17/cm.sup.3 to 9×10.sup.17/cm.sup.3. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 μm to 1.1 μm. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p.sup.+-type high-concentration region is provided. Each p.sup.+-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.