Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

A method of forming an electrode in accordance with an exemplary embodiment includes a process of forming a mask pattern on one surface of a base to expose a partial area of the one surface of the base by using a mask material that is polymer including an end tail having at least one bonding structure of covalent bond and double bond, a process of loading the base on which the mask pattern is formed into a chamber, and a process of forming a conductive layer containing copper on the exposed one surface of the base by using an atomic layer deposition method that alternately injects a source material containing copper and a reactive material that reacts with the source material into the chamber.

Thus, according to the method of forming an electrode in accordance with an exemplary embodiment, a thin-film caused by a material for forming an electrode is not formed on a surface of the mask pattern. Therefore, a residue is not remained when the mask pattern is removed to prevent a defect caused by the residue from being generated.

In a plasma processing method for plasma etching a silicon film or polysilicon film containing boron, the polysilicon film containing boron is etched by using a mixed gas of a halogen gas, a fluorine-containing gas, and a boron trichloride gas. According to plasma processing method, it is possible to improve the etching rate and reduce etching defects when plasma etching a silicon film or polysilicon film containing boron.

Provided is a plasma processing method capable of improving an etching selectivity of a material to be etched with respect to a mask material and reducing a roughness of a side wall of a mask pattern. The plasma processing method of selectively depositing a deposition film on the mask material with respect to the material to be etched includes controlling an etching parameter so that an incubation time of the mask material is shorter than an incubation time of the material to be etched.

Provided is a method of high-density pattern forming, which includes: providing a substrate; forming a hard mask layer on the substrate; forming a sacrificial layer on the hard mask layer; forming photoresists arranged at intervals on the sacrificial layer; etching the sacrificial layer to enable the sacrificial layer to form a mandrel corresponding to the photoresist one by one, wherein a cross-sectional size of the mandrel gradually decreases from an end of the mandrel away from the hard mask layer to an end close to the hard mask layer; forming an isolation layer on the mandrel; removing the isolation layer on the top of the mandrel, the isolation layer covering the hard mask layer, and the mandrel to form an isolation sidewall pattern; and transferring the isolation sidewall pattern to the hard mask layer.

A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

Methods, apparatus, and systems are provided herein for processing a substrate. Generally, the processing involves Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP) techniques. The disclosed techniques provide a novel process flow that reduces defects by ensuring that cores are not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the cores are removed from the substrate prior to cleaning and transfer.

Provided is a semiconductor structure and a method for manufacturing the same. The method includes forming a spin on hard mask layer on a base, active areas arranged at intervals in the base, bit lines arranged at intervals and extending in a first direction on the base, each bit line electrically connected to at least one active area, and the spin on hard mask layer filled between the bit lines and covering the bit lines; removing part of the spin on hard mask layer to form first trenches arranged at intervals and extending in a second direction; forming first sacrificial layers in the first trenches; removing the spin on hard mask layer between the first sacrificial layers to form second trenches; forming first supporting layers in the second trenches; removing the first sacrificial layers and elongating the first trenches located between adjacent bit lines to the active areas.

A thin film transistor and a method for manufacturing the same, an array substrate and an electronic device. The thin film transistor includes a gate, a gate insulator, an active layer, a source and a drain. A protective structure is disposed on a side of the source and the drain close to the gate.

The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device.