Provided are a silicon-on-insulator structure having bipolar stress and a manufacturing method therefor. The manufacturing method comprises providing a composite substrate, wherein the composite substrate has a silicon substrate layer, a buried oxide layer and a silicon-on-insulator layer sequentially from bottom to top, epitaxially growing a silicon germanium layer on an upper surface of the silicon-on-insulator layer; depositing a hard mask layer to cover a portion of the silicon germanium layer corresponding to an N-type MOS transistor region; depositing a surface oxide layer to cover the silicon germanium layer and the hard mask layer; performing a high temperature annealing treatment so that a portion of the silicon-on-insulator layer corresponding to a P-type MOS transistor region is converted into a silicon-germanium-on-insulator layer, and the portion corresponding to the N-type MOS transistor region is converted into a tensile stress silicon-on-insulator layer.

Provided are a silicon-on-insulator structure having bipolar stress and a manufacturing method therefor. The manufacturing method comprises providing a composite substrate, wherein the composite substrate has a silicon substrate layer, a buried oxide layer and a silicon-on-insulator layer sequentially from bottom to top, epitaxially growing a silicon germanium layer on an upper surface of the silicon-on-insulator layer; depositing a hard mask layer to cover a portion of the silicon germanium layer corresponding to an N-type MOS transistor region; depositing a surface oxide layer to cover the silicon germanium layer and the hard mask layer; performing a high temperature annealing treatment so that a portion of the silicon-on-insulator layer corresponding to a P-type MOS transistor region is converted into a silicon-germanium-on-insulator layer, and the portion corresponding to the N-type MOS transistor region is converted into a tensile stress silicon-on-insulator layer.

A semiconductor device has a super junction structure and includes a first semiconductor layer of the second conductive type disposed on the first column region and the second column region, a second semiconductor layer of the first conductive type disposed on the first semiconductor layer, a first semiconductor region of the first conductive type that is electrically connected to the first electrode and is disposed in a surface layer portion of the second semiconductor layer to be separated from the first semiconductor layer, and a second semiconductor region of the second conductive type that is electrically connected to the second electrode and that is disposed at least in the surface layer portion of the second semiconductor layer to be separated from the first semiconductor region and is electrically connected to the first semiconductor layer.

A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

An n-type region and a p-type region of a first parallel pn layer are arranged parallel to a base front surface, in a striped planar layout extending from an active region over an edge termination region. In the n-type region, a gate trench extending linearly along a first direction is provided. In an intermediate region, in a surface region on the base front surface side of the first parallel pn layer, a second parallel pn layer is provided. The second parallel pn layer is arranged having a repetition cycle shifted along a second direction a cell with respect to a repetition cycle of the n-type region and the p-type region of the first parallel pn layer. A gate trench termination portion terminates in the intermediate region between the active region and the edge termination region, and is covered by the p-type region of the second parallel pn layer.

Provided are a silicon-on-insulator structure having bipolar stress and a manufacturing method therefor. The manufacturing method comprises providing a composite substrate, wherein the composite substrate has a silicon substrate layer, a buried oxide layer and a silicon-on-insulator layer sequentially from bottom to top, epitaxially growing a silicon germanium layer on an upper surface of the silicon-on-insulator layer; depositing a hard mask layer to cover a portion of the silicon germanium layer corresponding to an N-type MOS transistor region; depositing a surface oxide layer to cover the silicon germanium layer and the hard mask layer; performing a high temperature annealing treatment so that a portion of the silicon-on-insulator layer corresponding to a P-type MOS transistor region is converted into a silicon-germanium-on-insulator layer, and the portion corresponding to the N-type MOS transistor region is converted into a tensile stress silicon-on-insulator layer.

Provided are a silicon-on-insulator structure having bipolar stress and a manufacturing method therefor. The manufacturing method comprises providing a composite substrate, wherein the composite substrate has a silicon substrate layer, a buried oxide layer and a silicon-on-insulator layer sequentially from bottom to top, epitaxially growing a silicon germanium layer on an upper surface of the silicon-on-insulator layer; depositing a hard mask layer to cover a portion of the silicon germanium layer corresponding to an N-type MOS transistor region; depositing a surface oxide layer to cover the silicon germanium layer and the hard mask layer; performing a high temperature annealing treatment so that a portion of the silicon-on-insulator layer corresponding to a P-type MOS transistor region is converted into a silicon-germanium-on-insulator layer, and the portion corresponding to the N-type MOS transistor region is converted into a tensile stress silicon-on-insulator layer.

A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

The present specification provides an electrode laminate including a substrate, an electrode provided on the substrate, and an auxiliary electrode electrically connecting to the electrode and has a laminated structure of a first layer having reflectivity of 80% or greater at a wavelength of 550 nm and a second layer having a higher etching rate compared to the first layer, wherein the auxiliary electrode is either provided between the electrode and the substrate, or provided so that the first layer of the auxiliary electrode adjoins at least part of the side surface of the electrode, and an organic light emitting device including the electrode laminate.