Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

A gateless P-N junction metrolog includes: a junction member including: a p-interface; and an n-interface disposed laterally and adjacent to the p-interface; and a p-n junction disposed at where the p-interface and n-interface contact; a drain electrode disposed on the junction member; a source electrode disposed on the junction member such that the source electrode is spaced apart from and opposing the drain electrode; an n-polymer disposed on the n-interface of the junction member; a p-polymer disposed on the p-interface of the junction member such that the n-polymer is interposed between the p-polymer and the n-interface; a mediation polymer disposed on the p-polymer such that the p-polymer is interposed between the mediation polymer and the junction member; and a mediator disposed in the mediation polymer and that receives electrons from the junction member in forming the p-interface.

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

A semiconductor device includes a substrate, a first insulating layer on the substrate, source and drain patterns at spaced-apart locations on the first insulating layer, and a channel layer having a transition metal therein, such as a transition metal dichalcogenide. The channel layer extends on the first insulating layer and between the source and drain patterns. A second insulating layer is also provided, which extends on the channel layer and has a thickness less than a thickness of the first insulating layer. A gate structure is provided, which extends on the second insulating layer, and opposite the channel layer. The channel layer may include at least one of MoS.sub.2, WS.sub.2, MoSe.sub.2, WSe.sub.2, MoSe.sub.2, WTe.sub.2, and ZrSe.sub.2.

A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and and a gate electrode surrounding the interfacial layer.

A field effect transistor structure is disclosed. The field effect transistor structure includes: a fin-shaped channel protruding from a substrate and extending in one direction; a source electrode on one side of the fin-shaped channel; a drain electrode separated from the source electrode with the fin-shaped channel therebetween; a gate insulating film surrounding side and upper surfaces of the fin-shaped channel; a gate electrode on the gate insulating film; and a two-dimensional semiconductor material layer between the gate insulating film and the gate electrode.

An approach to forming a field-effect transistor device formed with a two-dimensional material. The field-effect transistor device includes a channel composed of the two-dimensional material on a substrate and a high-k gate dielectric on the channel and extending under a sidewall spacer and around the sidewall spacer. The field-effect transistor includes a metal gate that is inside the high-k gate dielectric and over the channel. The source/drain is on a portion the two-dimensional material on the substrate. The source/drain abuts the sidewall spacer and is composed of a bi-layer metal.

Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.