Provided are a field effect transistor, an electronic apparatus including the same, and a method of manufacturing the field effect transistor. The field effect transistor may include a substrate; a gate electrode on the substrate; an insulating layer on the gate electrode; a source electrode on the insulating layer; a drain electrode apart from the source electrode; a channel between the source electrode and the drain electrode and including a two-dimensional (2D) material; a 2D material electrode bonding layer adjacent to the source electrode and the drain electrode; and a stressor adjacent to the 2D material electrode bonding layer. The stressor may be configured to apply a tensile strain to the 2D material electrode bonding layer.

An artificial two-dimensional (2D) material includes a layered atomic structure including a middle atomic layer, a lower atomic layer, and an upper atomic layer. The lower and upper atomic layers are disposed on lower and upper surfaces of the middle atomic layer respectively. The middle atomic layer is a 2D planar atomic structure formed of a transition metal. The lower and upper atomic layers are a 2D planar atomic structure formed of heterogeneous atoms. Atoms of the layered atomic structure are bound by chemical bonding.

A laminated body is provided in a circumferential shape with a gap formed in a part of a circumferential direction on a semiconductor layer. In the laminated body, a first insulating layer, a gate layer, a second insulating layer, and a drain layer are layered in this order from the semiconductor layer side. An impurity diffusion layer is formed on a surface of the semiconductor layer, and a backside electrode on a backside surface. The impurity diffusion layer extends from a position in contact with side walls in a channel space to an outside of the laminated body through a region corresponding to the gap on the surface of the semiconductor layer. A portion of the impurity diffusion layer beyond the laminated body is a contact region to which a wiring for applying a predetermined voltage is connected. A cover layer made of an insulating material is formed in an upper portion and a periphery of the annular portion including the laminated body and the gap.

By widening a terrace on a crystal surface on a bottom face of a recess by step flow caused by heating, a flat face is formed on the bottom face of the recess, a two-dimensional material layer made of a two-dimensional material is formed on the formed flat face, and then a device made of the two-dimensional material layer is produced.

A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.

Disclosed is a metal-semiconductor contact structure based on two-dimensional (2D) semimetal electrodes, including a semiconductor module and a metal electrode module, where the semiconductor module is a 2D semiconductor material, and the metal electrode module is a 2D semimetal material with no dangling bonds on its surface; the 2D semiconductor material and the 2D semimetal material are interfaced with a Van der Waals interface with a surface roughness of 0.01-1 nanometer (nm) and no dangling bonds on the surface, the 2D semiconductor material and the 2D semimetal material are spaced less than 1 nm apart.

According to one embodiment, a semiconductor device includes a supporter including a first surface, first, second, and third conductive parts, a semiconductor region, and an insulating part. A first direction from the first toward second conductive part is along the first surface. The semiconductor region includes first, second, and third partial regions. A second direction from the first toward second partial region is along the first surface and crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes a counter surface facing the second conductive part. A direction from the counter surface toward the third conductive part is along the second direction. The insulating part includes an insulating region. At least a portion of the insulating region is between the counter surface and the third conductive part.

The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

Described herein are integrated circuit devices with conductive regions formed from MX or MAX materials. MAX materials are layered, hexagonal carbides and nitrides that include an early transition metal (M) and an A group element (A). MX materials remove the A group element. MAX and MX materials are highly conductive, and their two-dimensional layer structure allows very thin layers to be formed. MAX or MX materials can be used to form several conductive elements of IC circuits, including contacts, interconnects, or liners or barrier regions for contacts or interconnects.