A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

A semiconductor device with low power consumption is provided. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of processing image data using a parameter. The image processing portion takes the image data from a frame memory and takes the parameter from the register. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller has a function of controlling power supply to the register, the frame memory, and the image processing portion.

A semiconductor device with low power consumption is provided. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of processing image data using a parameter. The image processing portion takes the image data from a frame memory and takes the parameter from the register. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller has a function of controlling power supply to the register, the frame memory, and the image processing portion.

An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.

Transistor devices having a doped buffer or sub-structure between an active channel and a substrate. In one embodiment, a p-type dopant, such as magnesium, zinc, carbon, beryllium, and the like, may be introduced in the formation of the sub-structure, wherein the dopant may act as a p/n junction at the active channel to source and drain interfaces and decrease the off-state leakage path. In another embodiment, the material used for the formation of the doped sub-structure may be substantially the same as the material, without the dopant, used for the formation of the active channel, such that no heterojunction will be formed which could result in crystalline imperfections.

Transistor devices having a doped buffer or sub-structure between an active channel and a substrate. In one embodiment, a p-type dopant, such as magnesium, zinc, carbon, beryllium, and the like, may be introduced in the formation of the sub-structure, wherein the dopant may act as a p/n junction at the active channel to source and drain interfaces and decrease the off-state leakage path. In another embodiment, the material used for the formation of the doped sub-structure may be substantially the same as the material, without the dopant, used for the formation of the active channel, such that no heterojunction will be formed which could result in crystalline imperfections.

A system having an electronic device. The electronic device has an array of chemically sensitive sensors. The sensors detect volatile organic compounds and have field effect transistors. The transistors have non-oxidized, functionalized silicon nanowires. The nanowires have surface Si atoms. The device has a plurality of functional groups that form a direct Si—C bond with the silicon nanowires, wherein Si is a surface Si atom and C is a carbon atom of the functional group. The functional groups are selected from the group consisting of: alkyl, cycloalkyl, alkenyl, alkynyl, aryl, heterocyclyl, heteroaryl, alkylaryl, alkylalkenyl, alkylalkynyl, alkylcycloalkyl, alkylheterocyclyl and alkylheteroaryl groups, and derivatives thereof, wherein said functional groups are other than methyl and 1-butyl. The plurality of functional groups are attached to 50-100% of the surface Si atoms.

A system having an electronic device. The electronic device has an array of chemically sensitive sensors. The sensors detect volatile organic compounds and have field effect transistors. The transistors have non-oxidized, functionalized silicon nanowires. The nanowires have surface Si atoms. The device has a plurality of functional groups that form a direct Si—C bond with the silicon nanowires, wherein Si is a surface Si atom and C is a carbon atom of the functional group. The functional groups are selected from the group consisting of: alkyl, cycloalkyl, alkenyl, alkynyl, aryl, heterocyclyl, heteroaryl, alkylaryl, alkylalkenyl, alkylalkynyl, alkylcycloalkyl, alkylheterocyclyl and alkylheteroaryl groups, and derivatives thereof, wherein said functional groups are other than methyl and 1-butyl. The plurality of functional groups are attached to 50-100% of the surface Si atoms.

A field effect transistor (FET) with a graphene layer as a channel layer is disclosed. The FET provides two gate electrodes, one of which receives the gate bias, while, the other receives a reference bias. An intermediate electrode made of ohmic metal to the graphene layer is provided between the two gate electrodes. The second gate electrode receiving the reference bias suppresses the hole injection into the channel beneath the first gate electrode.

A method of fabricating a semiconductor device comprises forming a dielectric layer above a substrate, the dielectric layer including a fixed dielectric portion and a proof mass portion, forming a source region and a drain region in the substrate, forming a gate electrode in the proof mass portion, and releasing the proof mass portion, such that the proof mass portion is movable with respect to the fixed dielectric portion and the gate electrode is movable with the proof mass portion relative to the source region and the drain region.