A semiconductor device includes a cooling base board and an insulated circuit substrate. On a front surface of an insulated board on the insulated circuit substrate, a high potential circuit pattern on which a semiconductor chip is mounted, an intermediate potential circuit pattern on which a semiconductor chip is mounted, a low potential circuit pattern, and a control circuit pattern are disposed so as to straddle a center line of the cooling base board. The intermediate potential circuit pattern includes a second chip mounting region, an output wiring connection region and an interconnect wiring region that form a U-shaped portion in which the high potential circuit pattern having a semiconductor chip thereon is disposed. The control circuit pattern is disposed so as to straddle the center line and faces the opening of the U-shaped portion.

A cell structure of a silicon carbide MOSFET device, comprising a drift region (3) located on a substrate layer (2), a second conducting type well region (4) and a first JFET region (51) that are located in the drift region (3), an enhancement region located within a surface of the well region (4), a gate insulating layer (8) located on a first conducting type enhancement region (6), the well region (4) and the first JFET region (51) and being in contact therewith at the same time, a gate (9) located on the gate insulating layer, source metal (10) located on the enhancement region, Schottky metal (11) located on a second conducting type enhancement region (7) and the drift region (3), a second JFET region (52) located on a surface of the drift region (3) between the Schottky metals (11), and drain metal (12).

A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

A manufacturing method for a semiconductor element includes a step of forming a mask partly having an opening and configured to cover a surface of a base substrate, and a step of forming a semiconductor layer containing a predetermined semiconductor material by inducing epitaxial growth along the mask from the surface of the base substrate exposed from an opening. A surface on the side closer to the semiconductor layer in the mask is formed of an amorphous first material that does not contain an element to serve as a donor or an acceptor in the predetermined semiconductor material.

This disclosure relates to a synaptic component for a neural network having a layer of a semiconductor and a source electrode connected to the semiconducting layer and a drain electrode connected to the semiconducting layer, wherein the source electrode is spatially separated from the drain electrode, wherein the source electrode and the semiconducting layer form a Schottky diode, wherein the source electrode is separated from a first gate electrode by ferroelectric material. This disclosure further relates to a method for operating a synaptic component according to the disclosure in which the first Schottky diode is connected in reverse direction and an electric voltage is applied on the first gate electrode in a pulsed manner.

This disclosure relates to a synaptic component for a neural network having a layer of a semiconductor and a source electrode connected to the semiconducting layer and a drain electrode connected to the semiconducting layer, wherein the source electrode is spatially separated from the drain electrode, wherein the source electrode and the semiconducting layer form a Schottky diode, wherein the source electrode is separated from a first gate electrode by ferroelectric material. This disclosure further relates to a method for operating a synaptic component according to the disclosure in which the first Schottky diode is connected in reverse direction and an electric voltage is applied on the first gate electrode in a pulsed manner.

A semiconductor has a layer of a first conductivity type with a main surface, a trench separation structure which includes a separation trench formed in the main surface, a separation insulating film that covers a wall surface of the separation trench and a separation electrode that is embedded in the separation trench across the separation insulating film, the trench separation structure demarcating an outer region and an active region in the main surface, a floating region of a second conductivity type which is formed in an electrically floating state at a surface layer portion of the main surface along the trench separation structure in the outer region, and a Schottky electrode which is electrically connected to the separation electrode such as to retain the floating region in the electrically floating state in the outer region and which forms a Schottky junction with the main surface in the active region.

A Ga.sub.2O.sub.3-based semiconductor device includes a Ga.sub.2O.sub.3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga.sub.2O.sub.3-based crystal layer.

A Ga.sub.2O.sub.3-based semiconductor device includes a Ga.sub.2O.sub.3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga.sub.2O.sub.3-based crystal layer.