A solar cell comprising a silicon substrate and a layered structure arranged on a surface of the silicon substrate, the layered structure comprising; a first layer comprising a percentage of crystalline material arranged within an amorphous matrix, the first layer being arranged on the surface of the silicon substrate; a second layer comprising a percentage of crystalline material arranged within an amorphous matrix, the second layer being interposed between the first layer and the surface of the silicon substrate; wherein the percentage of crystalline material in the first layer is greater than the percentage of crystalline material in the second layer.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as pillars and/or holes, effectively increase the effective absorption length resulting in a greater absorption of the photons. Using microstructures for absorption enhancement for silicon photodiodes and silicon avalanche photodiodes can result in bandwidths in excess of 10 Gb/s at photons with wavelengths of 850 nm, and with quantum efficiencies of approximately 90% or more.

A photovoltaic device includes a first contact and a hybrid absorber layer. The hybrid absorber layer includes a chalcogenide layer and a semiconductor layer in contact with the chalcogenide layer. A buffer layer is formed on the absorber layer, and a transparent conductive contact layer is formed on the buffer layer.

A photovoltaic device includes a first contact and a hybrid absorber layer. The hybrid absorber layer includes a chalcogenide layer and a semiconductor layer in contact with the chalcogenide layer. A buffer layer is formed on the absorber layer, and a transparent conductive contact layer is formed on the buffer layer.

The present disclosure pertains to the field of back contact heterojunction cell technologies, and particularly relates to a mask-layer-free hybrid passivation back contact cell and a fabrication method thereof; the method includes: S101: providing a silicon wafer substrate; S102: sequentially forming a first semiconductor layer and a mask layer on a back surface of the silicon wafer substrate, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer; S103: performing first etching on the first semiconductor layer on the obtained back surface to form first opening regions W.sub.1; S104: forming a textured surface in the first opening region W.sub.1 on the back surface by texturing and cleaning; S105: removing the mask layer; S106: forming a second semiconductor layer on the obtained back surface; and S107: performing second etching on a polished region of the obtained back surface.

The present disclosure pertains to the field of back contact heterojunction cell technologies, and particularly relates to a mask-layer-free hybrid passivation back contact cell and a fabrication method thereof; the method includes: S101: providing a silicon wafer substrate; S102: sequentially forming a first semiconductor layer and a mask layer on a back surface of the silicon wafer substrate, wherein the first semiconductor layer includes a tunneling oxide layer and a first doped polycrystalline layer; S103: performing first etching on the first semiconductor layer on the obtained back surface to form first opening regions W.sub.1; S104: forming a textured surface in the first opening region W.sub.1 on the back surface by texturing and cleaning; S105: removing the mask layer; S106: forming a second semiconductor layer on the obtained back surface; and S107: performing second etching on a polished region of the obtained back surface.

A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.

A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.

A method for manufacturing a solar cell can include forming a tunneling layer on first and second surfaces of a semiconductor substrate, the tunneling layer including a dielectric material; forming a polycrystalline silicon layer on the tunnel layer at the first surface and on the second surface of the semiconductor substrate; removing portions of the tunnel layer and the polycrystalline silicon layer formed at the first surface of the semiconductor substrate; forming a doping region at the first surface of the semiconductor substrate by diffusing a dopant; forming a passivation layer on the polycrystalline silicon layer at the second surface of the semiconductor substrate; and forming a second electrode connected to the polycrystalline silicon layer by penetrating through the passivation layer.