A semiconductor device includes a silicon substrate and a detection element and p-type and n-type MOS transistors, which are arranged on the silicon substrate, wherein the detection element includes a semiconductor layer, electrodes, and a Schottkey barrier disposed therebetween, the semiconductor layer is arranged just above a layer having the same composition and height as those of an impurity diffusion layer in the source or drain of the p-type or n-type MOS transistor, a region, in the silicon substrate, having the same composition and height as those of a channel region, in the silicon substrate, just below a gate oxide film of the p-type MOS transistor or the n-type MOS transistor, or a region, in the silicon substrate, having the same composition and height as those of a region just below a field oxide film disposed between the p-type and the n-type MOS transistor.

A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (5.sub.1, 5.sub.2: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.

A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (5.sub.1, 5.sub.2: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.

A semiconductor device capable of high speed operation is provided. Further, a semiconductor device in which change in electric characteristics due to a short channel effect is hardly caused is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed by self-aligned process in which one or more elements selected from Group 15 elements are added to the semiconductor layer with the use of a gate electrode as a mask. The source region and the drain region can have a wurtzite crystal structure.

An optical device including a two-dimensional material and a method of manufacturing the same are provided. The optical device may include a barrier stack formed on a bottom channel layer, a top channel layer formed on the barrier stack, a drain electrode connected to the bottom channel layer, a source electrode formed on a substrate. The barrier stack may include two or more barrier layers, and one or more channel units at least partially interposing between the barrier layers. Channel units connected to the drain electrode and channel units connected to the source electrode may be formed, in an alternating sequence, between barrier layers included in the barrier stack. The barrier layers may each have a thickness which is less than a distance which may be traveled by electrons and holes generated by photo absorption prior to recombination. As a result, the optical device may provide improved photo separation efficiency.

A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.

A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques.

A method and apparatus, the method comprising: forming first electrode portions on a substrate; providing a sheet of two dimensional material overlaying at least part of the first electrode portions; forming second electrode portions on a superstrate; positioning the superstrate overlaying the substrate so that the second electrode portions are aligned with the first electrode portions; and laminating the substrate and the superstrate together so that the sheet of two dimensional material is positioned between the aligned first electrode portions and the second electrode portions.

A method and apparatus, the method comprising: forming first electrode portions on a substrate; providing a sheet of two dimensional material overlaying at least part of the first electrode portions; forming second electrode portions on a superstrate; positioning the superstrate overlaying the substrate so that the second electrode portions are aligned with the first electrode portions; and laminating the substrate and the superstrate together so that the sheet of two dimensional material is positioned between the aligned first electrode portions and the second electrode portions.

A monolithic photo detector device disposed on a bulk substrate, comprising a photo detector disposed integrated in the bulk substrate including: (1) a p-type doped impurity region extending along a first direction in the major surface of the substrate and receiving a first voltage, (2) first and second gates being spaced apart from each other and extending in the first direction over the major surface of the substrate, wherein the gates receives a second voltage, (3) an n-type doped impurity region, extending along the first direction in the major surface of the substrate and receiving a third voltage; and (4) a light absorbing region, disposed between the second doped impurity region and the first gate. The device also includes control circuitry, integrated in the substrate to generate the first, second and third voltages that control an operating state of the detector.