A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.

An optical sensor includes: a photosensitive layer that absorbs incident light to generate a first carrier with a first polarity and a second carrier with a second polarity different from the first polarity; a channel layer that is electrically connected to the photosensitive layer and that conducts the first carrier that has moved from the photosensitive layer; a counter electrode facing the channel layer through the photosensitive layer; an insulating layer positioned between the photosensitive layer and the counter electrode; and a source electrode and a drain electrode each electrically connected to the channel layer.

An optical sensor includes: a photosensitive layer that absorbs incident light to generate a first carrier with a first polarity and a second carrier with a second polarity different from the first polarity; a channel layer that is electrically connected to the photosensitive layer and that conducts the first carrier that has moved from the photosensitive layer; a counter electrode facing the channel layer through the photosensitive layer; an insulating layer positioned between the photosensitive layer and the counter electrode; and a source electrode and a drain electrode each electrically connected to the channel layer.

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

An image sensor device includes nanostructures for improving light absorption efficiency. The image sensor device includes a substrate, a light absorption region, and a nanostructure array. The light absorption region is over the substrate. The nanostructure array us over the light absorption region. The nanostructure array includes a plurality of nanostructures repeatedly arranged from a top view.

A through electrode substrate includes a substrate provided with a through hole; a through electrode having a sidewall portion extending along a sidewall of the through hole, and a first portion positioned on a first surface of the substrate and connected to the sidewall portion; an inorganic film that at least partially covers the first portion of the through electrode from the first side and is provided with an opening positioned on the first portion; and a first wiring structure including at least a first wiring layer having an insulation layer that is positioned to the first side of the inorganic film and includes at least an organic layer provided with an opening communicating with the opening of the inorganic film, and an electroconductive layer connected to the first portion of the through electrode through the opening of the inorganic film and the opening of the insulation layer.

A sensor for discriminating between wavelength regions in an electromagnetic spectrum is disclosed. The sensor comprising a substrate, a sensing element supported on a surface of the substrate, and at least one pair of terminal electrodes disposed on the substrate surface in mutually spaced apart and opposing relation, and in electrical contact with the sensing element, wherein the sensing element is responsive to electromagnetic radiation to yield a change in photocurrent measured between the terminal electrodes as a function of an intensity of the electromagnetic radiation impinging thereon, wherein a positive dependency on the intensity corresponds to a first wavelength region and a negative dependency on the intensity corresponds to a second wavelength region.

A photoelectric conversion device has an isolation structure. First and second isolation portions are provided between first and second photoelectric conversion elements. The first isolation portion extends from a first plane of a semiconductor layer to a position corresponding to at least a quarter of a length from the first plane to a second plane of the semiconductor layer. The second isolation portion extends from the second plane of the semiconductor layer to a position corresponding to at least a quarter of the length from the first plane to the second plane.

A photoelectric conversion device has an isolation structure. First and second isolation portions are provided between first and second photoelectric conversion elements. The first isolation portion extends from a first plane of a semiconductor layer to a position corresponding to at least a quarter of a length from the first plane to a second plane of the semiconductor layer. The second isolation portion extends from the second plane of the semiconductor layer to a position corresponding to at least a quarter of the length from the first plane to the second plane.

Depositing gallium nitride and carbon (GaN:C) (e.g., in the form of composite layers) when forming a gallium nitride drain of a transistor provides a buffer between the gallium nitride of the drain and silicon of a substrate in which the drain is formed. As a result, gaps and other defects caused by lattice mismatch are reduced, which improves electrical performance of the drain. Additionally, current leakage into the substrate is reduced, which further improves electrical performance of the drain. Additionally, or alternatively, implanting silicon in an aluminum nitride (AlN) liner for a gallium nitride drain reduces contact resistance at an interface between the gallium nitride and the silicon. As a result, electrical performance of the transistor is improved.