This invention relates to a patterned substrate for light emitting diode. The patterned substrate includes a surface having a plurality of protrusive structures, wherein each of the protrusive structures includes an upper portion and a lower portion. The surface of the lower portion is a conical surface, and has at least one first zone and at least one second zone. The first zone and the second zone are alternately arranged, wherein the first zone has one or more first projections.

The invention relates, inter alia, to a method for producing a plurality of semiconductor chips, the method comprising the following steps: providing a substrate (1); applying a semiconductor layer sequence (2) to the substrate (1); generating a plurality of recesses (6) in the semiconductor layer sequence (2) on the side of the semiconductor layer sequence (2) that is facing away from the substrate (1); detaching the substrate (1) from the semiconductor layer sequence (2); thinning the semiconductor layer sequence (2) on the side that was facing the substrate (1) prior to detaching the substrate (1).

A process allowing at least one semipolar layer of nitride to be obtained, which layer is obtained from a least one among gallium, indium and aluminum on a top surface of a single-crystal layer based on silicon, wherein the process comprises the following steps: etching, from the top surface of the single-crystal layer, a plurality of parallel grooves comprising at least two opposite inclined facets, at least one of two opposite facets having a crystal orientation; masking the top surface of the single-crystal layer such that the facets having a crystal orientation are not masked; and epitaxial growth of the semipolar layer of nitride from the not masked facets; wherein the etching is carried out on a stack comprising the single-crystal layer and at least one stop layer that is surmounted by the single-crystal layer and wherein the etching etches the single-crystal layer selectively with respect to the stop layer so that the etching stops on contact with the stop layer.

An LED subpixel can be provided with a reflector layer that controls viewing angles. After formation of an array of nanowires including first conductivity type cores and active layers, a second conductivity type semiconductor material layer, a transparent conductive oxide layer, and a dielectric material layer are sequentially formed. An opening is formed through the dielectric material layer over the array of nanowires. The reflector layer can be formed around the array of nanowires and through the opening in the dielectric material layer on the transparent conductive oxide layer. A conductive bonding structure is formed in electrical contact with the reflector layer.

A display apparatus is provided. The display apparatus includes a substrate, a transistor, a metal layer, and a light-emitting diode. The transistor is disposed on the substrate. The metal layer is disposed on the transistor and electrically connected to the transistor, wherein a first distance is between the upper surface of the metal layer and the substrate in a direction perpendicular to the substrate. The light-emitting diode is disposed on the metal layer, wherein the light-emitting diode includes a light-emitting diode body and an electrode, the light-emitting diode body is electrically connected to the metal layer via the electrode, the light-emitting diode body has a first surface and a second surface opposite to the first surface, the first surface and the second surface are parallel to the substrate, and in the direction above, a second distance is between the first surface and the second surface, wherein the ratio of the second distance to the first distance is greater than or equal to 0.25 and less than or equal to 6.

A light emitting diode with a zinc oxide layer and a method of fabricating the same are disclosed. The light emitting diode includes: a light emitting structure including a gallium nitride based first conductivity type semiconductor layer, a gallium nitride based second conductivity type semiconductor layer, and an active layer interposed therebetween; and a ZnO transparent electrode layer disposed on the second conductivity type semiconductor layer, wherein the ZnO transparent electrode layer comprises a ZnO seed layer and a ZnO bulk layer formed on the ZnO seed layer, wherein the ZnO bulk layer is porous compared to the ZnO seed layer, wherein an interface between the ZnO seed layer and the second conductivity type semiconductor layer is flatter than an interface between the ZnO seed layer and the ZnO bulk layer, and wherein the interface between the ZnO seed layer and the ZnO bulk layer has an irregular concavo-convex shape.

Embodiments generally relate to multi-layer buffer structures on silicon. One method for forming such a structure comprises: providing a (111) silicon substrate; using ALD to deposit a first layer of AlN on the substrate; using first and second precursor materials at a first V-III ratio to deposit a plurality of AlN islands forming a second layer on the first layer; using the first and second precursor materials at a second V-III ratio, to deposit a third layer of AlN overlying and in contact with the islands and the first layer between the islands, forming domains; and using the first and second precursor materials at a third V-III ratio, to deposit a fourth layer of AlN on the third layer. All depositions occur at one predetermined temperature range. The fourth layer is characterized by a fourth layer top surface that is anatomically smooth.

Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

A multilayer structure including a hexagonal epitaxial layer, such as GaN or other group III-nitride (III-N) semiconductors, a <111> oriented textured layer, and a non-single crystal substrate, and methods for making the same. The textured layer has a crystalline alignment preferably formed by the ion-beam assisted deposition (IBAD) texturing process and can be biaxially aligned. The in-plane crystalline texture of the textured layer is sufficiently low to allow growth of high quality hexagonal material, but can still be significantly greater than the required in-plane crystalline texture of the hexagonal material. The IBAD process enables low-cost, large-area, flexible metal foil substrates to be used as potential alternatives to single-crystal sapphire and silicon for manufacture of electronic devices, enabling scaled-up roll-to-roll, sheet-to-sheet, or similar fabrication processes to be used. The user is able to choose a substrate for its mechanical and thermal properties, such as how well its coefficient of thermal expansion matches that of the hexagonal epitaxial layer, while choosing a textured layer that more closely lattice matches that layer. Electronic devices such as LEDs can be manufactured from such structures. Because the substrate can act as both a reflector and a heat sink, transfer to other substrates, and use of external reflectors and heat sinks, is not required, greatly reducing costs. Large area devices such as light emitting strips or sheets may be fabricated using this technology.

Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H.sub.2 and/or NH.sub.3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.