Patent classifications
H01L33/007
SEED WAFER FOR GaN THICKENING USING GAS- OR LIQUID-PHASE EPITAXY
Embodiments relate to fabricating a wafer including a thin, high-quality single crystal GaN layer serving as a template for formation of additional GaN material. A bulk ingot of GaN material is subjected to implantation to form a subsurface cleave region. The implanted bulk material is bonded to a substrate having lattice and/or Coefficient of Thermal Expansion (CTE) properties compatible with GaN. Examples of such substrate materials can include but are not limited to AlN and Mullite. The GaN seed layer is transferred by a controlled cleaving process from the implanted bulk material to the substrate surface. The resulting combination of the substrate and the GaN seed layer, can form a template for subsequent growth of overlying high quality GaN. Growth of high-quality GaN can take place utilizing techniques such as Liquid Phase Epitaxy (LPE) or gas phase epitaxy, e.g., Metallo-Organic Chemical Vapor Deposition (MOCVD) or Hydride Vapor Phase Epitaxy (HVPE).
PROCESS FOR MANUFACTURING A PLURALITY OF CRYSTALLINE SEMICONDUCTOR ISLANDS HAVING A VARIETY OF LATTICE PARAMETERS
A method for manufacturing a plurality of crystalline semiconductor islands having different lattice parameters includes providing a relaxation substrate comprising a support and a flow layer on the support that includes first and second groups of blocks having different viscosities at a relaxation temperature. The relaxation substrate also comprises a plurality of strained crystalline semiconductor islands on the flow layer, the islands of a first group being located on the first group of blocks and islands of a second group being located on the second group of blocks. The relaxation substrate is then heat treated at a relaxation temperature higher than or equal to the glass transition temperature of at least one block of the flow layer to cause differentiated lateral expansion of the first and second groups of islands such that the first and second groups of relaxed islands then have different lattice parameters.
HIGH EFFICIENT MICRODEVICES
A microdevice structure comprising at least part of an edge of a microdevice is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.
ScAlMgO4 SINGLE CRYSTAL SUBSTRATE AND METHOD FOR PRODUCING THE SAME
A ScAlMgO.sub.4 single crystal substrate having less collapse of crystal orientation, and a method for producing the single crystal substrate. A ScAlMgO.sub.4 single crystal substrate is provided, wherein, when a center of the substrate is designated as coordinates (0,0) and a measurement beam width is set to 1 [mm]7 [mm] to conduct analysis according to an X-ray diffraction method at respective coordinate positions of (x.sub.m,0) to (x.sub.m,0) at an interval of 1 [mm] in an x-axis direction and (0,y.sub.n) to (0,y.sub.n) at an interval of 1 mm in a y-axis direction, wherein m and n are each an integer falling within the range so that the measurement beam is not stuck out from the substrate, a worst value of a full width at half maximum of a rocking curve at each of the coordinate positions is less than 20 [sec.].
Light emitting diode and method of fabricating the same
Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.
Nitride underlayer and fabrication method thereof
A fabrication method of a nitride underlayer structure includes, during AlN layer sputtering with PVD, a small amount of non-Al material is doped to form nitride with decomposition temperature lower than that of AlN. A high-temperature annealing is then performed. After annealing, the AlN layer has a rough surface with microscopic ups and downs instead of a flat surface. By continuing AlGaN growth via MOCVD over this surface, the stress can be released via 3D-2D mode conversion, thus improving AlN cracks.
Double mesa large area AlInGaBN LED design for deep UV and other applications
Methods are provided for forming AlInGaBN material. The method can include growing an AlInGaBN layer on a substrate; removing a portion of the AlInGaBN layer from the substrate to define a plurality of AlInGaBN islands on the substrate; and growing a highly doped-AlInGaBN layer on each of the AlInGaBN islands.
Resonant optical cavity light emitting device
Resonant optical cavity light emitting devices are disclosed, where the device includes a substrate, a first spacer region, a light emitting region, a second spacer region, and a reflector. The light emitting region is configured to emit a target emission deep ultraviolet wavelength, and is positioned at a separation distance from the reflector. The reflector may have a metal composition comprising elemental aluminum or may be a distributed Bragg reflector. The device has an optical cavity comprising the first spacer region, the second spacer region and the light emitting region, where the optical cavity has a total thickness less than or equal to K.Math./n. K is a constant ranging from 0.25 to less than 1, is the target wavelength, and n is an effective refractive index of the optical cavity at the target wavelength.
Manufacturing method for light emitting diode crystal grains using adhesive layer on auxiliary substrate to fill gaps between light emitting diode crystal grains
A method for manufacturing light emitting diode crystal grains includes steps of providing a first substrate; forming a buffer layer on the first substrate; forming a UV blocking layer on buffer layer; and forming a plurality of light emitting diode crystal grains on the buffer layer. The emitting diode crystal grains together form a wafer. An auxiliary substrate is provided and coated with an adhesive layer. The auxiliary substrate is pressed to the wafer, the adhesive layer fills gaps between the light emitting diode crystal grains, and solidifies the adhesive layer. The second surface is irradiated and gasified. The first substrate is thus separated from the UV blocking layer and the adhesive layer is dissolved, thus achieving a plurality of light-emitting diode crystal grains.
Optoelectronic device and method for making the same
An optoelectronic device and method of manufacturing an optoelectronic device are disclosed. The optoelectronic device includes a substrate; a semiconductor comprising an n-type layer disposed on the substrate, a p-type layer disposed on the n-type layer, and an active layer disposed between the n-type layer and the p-type layer; a transition layer disposed on the substrate and located between the n-type layer and the substrate, the transition layer including an oxygenated IIIA-transition metal nitride; and a p-contact layer disposed on the p-type layer of the semiconductor.