A nitride light-emitting diode (LED) fabrication method includes: providing a glass substrate; stacking a buffer layer structure composed of circular SiAlN layers and AlGaN layers with the number of cycles 1-5; growing a non-doped GaN layer, an N-type layer, a quantum well layer and a P-type layer. By using the low-cost glass the substrate that has a mature processing technology, and growing a SiAlN and an AlGaN buffer layer thereon, lattice mismatch constant between the substance and the epitaxial layer can be improved. Therefore, photoelectric property of the LED can be improved.

A manufacturing method includes: providing a substrate in which a semiconductor layer including a light-emitting layer is located on a first substrate; forming a metal layer on the semiconductor layer; bonding the semiconductor layer via the metal layer to a second substrate that includes a circuit that includes a circuit element is formed; forming a light-emitting element by patterning the semiconductor layer; forming a first wiring layer by patterning the metal layer; forming an insulating film that covers the light-emitting element and the first wiring layer; forming a first via that extends through the insulating film to the circuit; forming a second wiring layer on the insulating film; and connecting the light-emitting element and the circuit element electrically in series via the first wiring layer, the second wiring layer, and the first via.

Techniques, devices, and systems are disclosed and include LEDs with a first flat region, at a first height from an LED base and including a plurality of epitaxial layers including a first n-layer, a first active layer, and a first p-layer. A second flat region is provided, at a second height from the LED base and parallel to the first flat region, and includes at least a second n-layer. A sloped sidewall connecting the first flat region and the second flat region is provided and includes at least a third n-layer, the first n-layer being thicker than at least a portion of third n-layer. A p-contact is formed on the first p-layer and an n-contact formed on the second n-layer.

A sidewall light emitting ultraviolet light emitting diode and a method of manufacturing thereof are disclosed. A light emitting structure is formed in an active region recessed from a substrate surface, and the light emitting structure is formed by growth in a direction parallel to the surface of the substrate. Also, a reflective metal layer is formed above or below the light emitting structure such that ultraviolet light can be released in a second direction perpendicular to a first direction which is the growth direction of the light emitting structure.

Resonant optical cavity light emitting devices and method of producing such devices are disclosed. The device includes a substrate, a first spacer region, a light emitting region, a second spacer region, and a reflector. The light emitting region is configured to emit a target emission deep ultraviolet wavelength, and is positioned at a separation distance from the reflector. The reflector has a metal composition comprising elemental aluminum. Using a three-dimensional electromagnetic spatial and temporal simulator, it is determined if an emission output at an exit plane relative to the substrate meets a predetermined criterion. The light emitting region is placed at a final separation distance from the reflector, where the final separation distance results in the predetermined criterion being met.

A substrate wafer composed of a hexagonal single crystal material including a C crystalline plane, an A crystalline plane, and an M-axis direction includes a top surface is a C-axis plane; a first side connecting to the aforementioned top surface and being substantially a curve line viewing from the direction perpendicular to the aforementioned C crystalline plane and including a curvature center; and a second side connecting to the aforementioned first side; and wherein there is a line segment defined by a shortest distance between the aforementioned second side and the aforementioned curvature center, and the aforementioned line segment is not parallel with the aforementioned M-axis direction.

A gallium nitride based integrated circuit architecture includes a first electronic device including a first set of III-N epitaxial layers and a second electronic device including a second set of III-N epitaxial layers. The gallium nitride based integrated circuit architecture also includes one or more interconnects between the first electronic device and the second electronic device. The first electronic device and the second electronic device are disposed in a chip scale package.

Provided is a III nitride semiconductor light emitting device with improved reliability capable of maintaining light output power reliably as compared with conventional devices, and a method of producing the same. The III-nitride semiconductor light-emitting device comprising: a light emitting layer, a p-type electron blocking layer, a p-type contact layer, and a p-side electrode in this order. The p-type contact layer has a first p-type contact layer co-doped with Mg and Si in contact with the p-type electron blocking layer and a second p-type contact layer doped with Mg in contact with the p-side electrode.

A light emitting device is provided to include an n-type semiconductor layer, a p-type semiconductor layer, an active layer, and an electron blocking layer disposed between the p-type semiconductor layer and the active layer. The p-type semiconductor layer includes a hole injection layer, a p-type contact layer, and a hole transport layer. The hole transport layer includes a plurality of undoped layers and at least one intermediate doped layer disposed between the undoped layers. At least one of the undoped layers includes a zone in which hole concentration decreases with increasing distance from the hole injection layer or the p-type contact layer, and the intermediate doped layer is disposed to be at least partially overlapped with a region of the hole transport layer, the region having the hole concentration of 62% to 87% of the hole concentration of the p-type contact layer.

Electronic devices are formed on donor substrates and transferred to carrier substrates by forming bonding regions on the electronic devices and bonding the bonding regions to a carrier substrate. The transfer process may include forming anchors and removing sacrificial regions.