There is set forth herein, in one example, a device comprising: a detector surface; an array of sensing photodiodes formed in a semiconductor formation, wherein the semiconductor formation receives light from the detector surface; and a light separating structure intermediate the detector surface and a sensing photodiode of the array of sensing photodiodes.

The invention relates to an embodiment in which the textile component comprises at least one flexible thread that can be woven. A plurality of semiconductor columns are attached in or on the thread and are configured to generate radiation. Furthermore, a plurality of electrical lines are located in or on the thread, by means of which lines the semiconductor columns are electrically contacted. An average height (H) of the semiconductor columns in a direction transverse to a longitudinal direction (L) of the thread is at most 20% of an average diameter (D) of the thread.

A process for sputtering a plurality of integrated circuit (“IC”) units, the process having at least the steps of: applying a layer to a holding ring; cutting an array of apertures in the layer; transferring the holding ring to a template positioned within a placement station; aligning the array of apertures with an array of recesses in the template; delivering IC units to the holding ring, each IC unit corresponding to an aligned aperture and recess, and then; applying a sputtering process to the IC units engaged with the holding ring.

Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level, where the second level overlays the first level and includes a plurality of second transistors; a fourth metal layer overlaying the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level and has a diameter of less than 500 nm and greater than 5 nm, where the third metal layer is connected to provide a power or ground signal to at least one of the second transistors.

A carrier substrate to be used, when manufacturing a member for an electronic device on a surface of a substrate, by being bonded to the substrate, includes at least a first glass substrate. The first glass substrate has a compaction described below of 80 ppm or less. Compaction is a shrinkage in a case of subjecting the first glass substrate to a temperature raising from a room temperature at 100° C./hour and to a heat treatment at 600° C. for 80 minutes, and then to a cooling to the room temperature at 100° C./hour.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

The present disclosure relates to a semiconductor substrate manufacturing method including: forming a catalytic metal film composed of a transition metal on a main surface to be polished of a workpiece substrate composed of any one of diamond, silicon carbide, gallium nitride, and sapphire; and providing relative movement between the workpiece substrate on which the catalytic metal film has been formed and a polishing platen in an oxidant solution to remove a compound generated by chemical reaction of an active radical generated by reaction of the catalytic metal film and the oxidant solution and a surface atom on the main surface of the workpiece substrate to thereby polish the workpiece substrate. The manufacturing method further includes: bonding the polished workpiece substrate to a nitride semiconductor layer by room temperature bonding; and removing a support substrate and a resin adhesive layer.

A coupon wafer comprising a device coupon (110) for use in a micro-transfer printing process used to fabricate an optoelectronic device. The coupon wafer includes a wafer substrate (124), and the device coupon (110) is attached to the wafer substrate via a tether (122) and the tether (122) is formed from a dielectric material.

A highly reliable display apparatus is provided at a low cost. The display apparatus includes a light-emitting diode included in a pixel circuit, a transistor included in the pixel circuit, and a transistor included in a driver circuit of the pixel circuit, which are stacked to have an overlap region. With such a structure, the display apparatus can be downsized. In addition, in the display apparatus, a plurality of light-emitting diodes can be attached to a circuit board formed with a transistor and the like in one step. Consequently, the manufacturing cost of the display apparatus can be reduced.