Patent classifications
H01L2221/68363
3D SEMICONDUCTOR DEVICE AND STRUCTURE
A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, where the via includes tungsten, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.
DEVICE FOR TRANSFERRING ELECTRONIC COMPONENT AND METHOD FOR TRANSFERRING ELECTRONIC COMPONENT
A device for transferring electronic component, comprising: an energy source used to project an energy beam; a first frame used to carry a carrier loaded with electronic component; a second frame used to carry a substrate for receiving the aforesaid electronic component; a beam splitting element arranged between the first frame and the energy source; and a focusing device arranged between the first frame and the beam splitting element. The present invention also relates to a method of transferring electronic component. The device for transferring electronic component and the method for transferring electronic component of the present invention can be applied in the manufacturing process of display.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, a method for manufacturing a semiconductor device includes placing a semiconductor chip on a first surface of a support substrate, forming a first resin layer covering the semiconductor chip on the first surface, and forming a second resin layer on a second surface of the support substrate. The second surface is opposite the first surface. In some examples, the second resin layer can be formed to counteract or mitigate warpage of the support substrate that might otherwise result from use of the first resin layer.
HYBRID ELEMENT SUBSTRATE AND METHOD OF FABRICATING THE SAME
Provided is a method of fabricating a hybrid element substrate, the method including forming a plurality of first elements on a first substrate which is a silicon substrate or a silicon-on-insulator (SOI) substrate; forming a plurality of second elements on a second substrate which has a material different from a material of the first substrate; separating a plurality of second elements from the second substrate; primarily transferring the plurality of second elements onto a transfer substrate comprising a plurality of grooves by a fluidic self-assembly method such that the plurality of second elements are arranged in the plurality of grooves of the transfer substrate, respectively; and secondarily transferring, onto the first substrate, the plurality of second elements transferred onto the transfer substrate such that the plurality of second elements are next to the first elements on the first substrate and spaced apart from each other, or overlap upper portions of the first elements, respectively.
METHOD OF PICKING UP DIE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME
A method of picking up a die may include classifying a pickup region of a diced wafer, in which targeted pickup dies are placed, into first to n-th regions and performing a pickup step on dies in the first to n-th regions. The first region may include first dies, which are outermost dies of the targeted pickup dies. An (x+1)-th region may include regions, occupied by dies adjacent to at least one of x-th dies in an x-th region and proximate to a center of the pickup region in relation to the x-th region, n may be a natural number, and x may be an arbitrary natural number that is smaller than the n. The n-th region may have a rectangular shape, and a quantity of n-th dies in the n-th region in contact with a short side of the n-th region may be one or two.
SEMICONDUCTOR DIE ASSEMBLIES WITH SIDEWALL PROTECTION AND ASSOCIATED METHODS AND SYSTEMS
Semiconductor die assemblies with sidewall protection, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die with a low-k dielectric layer and a stack of semiconductor dies attached to the interface die. The semiconductor die assembly also includes a molding structure that protects sidewalls of the interface die and sidewalls of the semiconductor dies. In some embodiments, the semiconductor die assembly includes a passivation layer attached to the interface die opposite to the stack of semiconductor dies. Further, the passivation layer may include a sidewall surface coplanar with an outer sidewall surface of the molding structure. The passivation layer may include a ledge underneath the molding structure, which is uncovered by the interface die. The semiconductor die assembly may include a NCF material at the sidewalls of the stack of semiconductor dies, where the molding structure surrounds the NCF material.
3D semiconductor device and structure
A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, where the via includes tungsten, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.
Multi-step high aspect ratio vertical interconnect and method of making the same
A multi-step conductive interconnect (MSI) may comprise a first step of the MSI comprising a first end and a second end opposite the first end, a first height (Ha) and a first diameter (Da). A second step of the MSI may comprise a first end and a second end opposite the first end. The first end of the second step contacts the second end of the first step. The second step may comprise a second height (Hb) and a second diameter (Db). The MSI may comprise a height (H) and a height to width aspect ratio (H:Da) greater than or equal to 1.5:1. A sidewall of the first step may comprise an offset (O) with respect to a sidewall of the second step to form a disjointed sidewall profile. The offset O may be in a range of 0.1 μm-20 μm.
SEMICONDUCTOR LIGHT-EMITTING DEVICE SELF-ASSEMBLY APPARATUS AND METHOD
Discussed is a self-assembly apparatus of a semiconductor light emitting diode. The self-assembly apparatus can include a fluid chamber including a space to accommodate a fluid and semiconductor light emitting diodes having a magnetic metal, a magnet to apply a magnetic force to the semiconductor light emitting diodes in a state where an assembly surface of a board is submerged in the fluid, a power supply portion to induce an electric field between assembly electrodes provided on the board so that the semiconductor light emitting diodes become seated at predetermined positions of the board while the semiconductor light emitting diodes are moved by a change in a position of the magnet, and a repair portion disposed in the fluid chamber and to separate some of the semiconductor light emitting diodes seated on the board from the board. The repair portion can be configured to spray and suction the fluid.
Multi-step integrated circuit handling process and apparatus
One exemplary aspect relates to a process and apparatus for selectively changing adhesion strength between a flexible substrate and a carrier at specific locations to facilitate shipping and subsequent removal of the flexible substrate from the carrier. The process includes providing a flexible substrate comprising a plurality of integrated circuits thereon providing a carrier for the flexible substrate and adhering the flexible substrate to the carrier by creating an interface between the flexible substrate and the carrier. The process further includes changing the adhesion force between the flexible substrate and the carrier at selected locations by non-uniform treatment of the interface between the flexible substrate and the carrier with an electromagnetic radiation source (e.g. a laser, flashlamp, high powered LED, an infrared radiation source or the like) so as to decrease or increase the adhesion force between a portion of the flexible substrate and the carrier at the selected location.