A method for forming a chip package structure is provided. The method includes removing a first portion of a substrate to form a first recess in the substrate. The method includes forming a buffer structure in the first recess. A first Young's modulus of the buffer structure is less than a second Young's modulus of the substrate. The method includes forming a first wiring structure over the buffer structure and the substrate. The method includes bonding a chip package to the first wiring structure. The chip package has an interposer substrate and a chip structure over the interposer substrate, and a first corner of the interposer substrate and a second corner of the chip structure overlap the buffer structure in a top view of the chip package and the buffer structure.

Systems and methods are provided for transferring a remote frequency identification (RFID) inlay from a first substrate to a second substrate. An RFID inlay is secured to a first substrate with a first adhesive. The RFID inlay is brought into the vicinity of a second substrate and secured to the second substrate with a second adhesive. The RFID inlay is then dissociated from the first substrate. The RFID inlay may be dissociated from the first substrate by softening the first adhesive, such as by the application of heat or the application of a softening substance. Alternatively, the RFID inlay may be dissociated from the first substrate without softening the first adhesive, but rather by differential release, whereby a release force is applied between the two substrates, with the release force being greater than the release strength of the first adhesive, but less than the release strength of the second adhesive.

Systems and methods are provided for transferring a remote frequency identification (RFID) inlay from a first substrate to a second substrate. An RFID inlay is secured to a first substrate with a first adhesive. The RFID inlay is brought into the vicinity of a second substrate and secured to the second substrate with a second adhesive. The RFID inlay is then dissociated from the first substrate. The RFID inlay may be dissociated from the first substrate by softening the first adhesive, such as by the application of heat or the application of a softening substance. Alternatively, the RFID inlay may be dissociated from the first substrate without softening the first adhesive, but rather by differential release, whereby a release force is applied between the two substrates, with the release force being greater than the release strength of the first adhesive, but less than the release strength of the second adhesive.

A sealing structure including: a set of base members forming a sealed space; a through-hole which is formed in at least one of the base members, and communicates with the sealed space; and a sealing member that seals the through-hole. An underlying metal film including a bulk-like metal such as gold is provided on a surface of the base member provided with the through-hole. The sealing member seals the through-hole while being bonded to the underlying metal film, and includes: a sealing material which is bonded to the underlying metal film, and includes a compressed product of a metal powder of gold or the like, the metal powder having a purity of 99.9% by mass or more; and a lid-like metal film which is bonded to the sealing material, and includes a bulk-like metal such as gold. Further, the sealing material includes: an outer periphery-side densified region being in contact with an underlying metal film; and a center-side porous region being in contact with the through-hole. The densified region has a porosity of 10% or less in terms of an area ratio at any cross-section.

In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.

When picking a die from an adhesive tape, a collet of a pick arm is positioned at a distance over the die, the die being mounted on a first surface of the adhesive tape. A flow of air is then generated onto a second surface of the adhesive surface opposite to the first surface for blowing the adhesive tape to displace the die towards a die-holding surface of the collet. Thereafter, the die is retained on the die-holding surface of the collet while the adhesive tape separates from the die.

A source wafer for use in a micro-transfer printing process. The source wafer comprising: a wafer substrate; a photonic component, provided in a device coupon, the device coupon being attached to the wafer substrate via a release layer; and one or more etch stop layers, located between the photonic component and the wafer substrate.

A method of picking up and depositing optoelectronic semiconductor chips comprises generating electron-hole pairs in optoelectronic semiconductor chips, thereby generating a dipole electric field in the vicinity of the respective optoelectronic semiconductor chip, generating an electric field by a pick-up tool, and picking up the optoelectronic semiconductor chips during or after generation of the electron-hole pairs by the pick-up tool and depositing them at predetermined locations.

Disclosed are novel structures and methods for 3D CMOS integrated circuits built with vertical transistors. A gate extension is selectively patterned by first patterning a sacrificial dielectric disposed on a gate material. A 3D CMOS IC comprises vertical transistors of one type constructed in one level and those of an opposite type in another level. The gate of lower-level vertical transistors may be coupled to a top interconnect directly through a 3D gate contact or indirectly through an upper-level via and a lower-level contact. A common-gate coupling may be formed between vertical transistors in different levels through a strapping contact or a gate via. A common-drain coupling may be formed between vertical transistors in different levels by forming upper-level vertical transistor on a piece of conductive film disposed over lower-level vertical transistor with or without an intervening top contact for lower-level vertical transistor.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).