A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

A fan-out semiconductor package includes a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposite the active surface; an encapsulant encapsulating at least some portions of the first interconnection member and the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the semiconductor chip. The first interconnection member and the second interconnection member respectively include a plurality of redistribution layers electrically connected to the connection pads of the semiconductor chip, and the semiconductor chip has a groove defined in the active surface and between a peripheral edge of the semiconductor chip and the connection pads of the semiconductor chip.

Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.

Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump. The pad is disposed on the substrate. The protective layer is disposed on the substrate. The protective layer has a first opening exposing a portion of a surface of the pad. The convex patterns are disposed on the protective layer. The RDL is disposed on the convex patterns. The RDL extends from the pad to the convex patterns. The bump is disposed on the convex patterns.

A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.