A semiconductor device according to the present disclosure includes a board and a via. In the board, a wiring layer is embedded. The via extends in a depth direction from a main surface of the board to pierce through the wiring layer, and is connected to the wiring layer on a side peripheral surface.

Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip.

A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.

A semiconductor device includes a semiconductor layer that has a main surface, an electrode pad that is formed on the main surface, a rewiring that has a first wiring surface connected to the electrode pad and a second wiring surface positioned on a side opposite to the first wiring surface and being roughened, the rewiring being formed on the main surface such as to be drawn out to a region outside the electrode pad, and a resin that covers the second wiring surface on the main surface and that seals the rewiring.

In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed.