A semiconductor device includes a first semiconductor die, a second semiconductor die including a side surface bonded to the first semiconductor die, such that the second semiconductor die is perpendicular to the first semiconductor die, and a junction circuit for connecting the first semiconductor die to the second semiconductor die.

A display device includes a substrate, a plurality of light-emitting elements and a plurality of transistors provided to the substrate, a first organic insulating film that is provided covering the transistors and is in direct contact with at least one of a source electrode and a drain electrode of the transistors, an anode electrode provided on the first organic insulating film and electrically coupled to each of the light-emitting elements, a cavity formed in the first organic insulating film and recessed toward the substrate, and a reflective layer provided covering a side and a bottom of the cavity formed in the first organic insulating film

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

A conductive via structure includes a first dielectric layer, a conductive pad in the first dielectric layer, a second dielectric layer, and a redistribution layer. The second dielectric layer is disposed above the first dielectric layer and has an opening. The conductive pad is in the opening. The opening has a first width at a top surface of the second dielectric layer, a second width at a bottom surface of the second dielectric layer, and a third width between the top surface and the bottom surface of the second dielectric layer. A difference between the first and second width is in a range from about 3 um to about 6 um. The redistribution layer extends from the top surface of the second dielectric layer to the conductive pad. The third width is gradually decreased from the top surface to the bottom surface of the second dielectric layer.

A conductive via structure includes a first dielectric layer, a conductive pad in the first dielectric layer, a second dielectric layer, and a redistribution layer. The second dielectric layer is disposed above the first dielectric layer and has an opening. The conductive pad is in the opening. The opening has a first width at a top surface of the second dielectric layer, a second width at a bottom surface of the second dielectric layer, and a third width between the top surface and the bottom surface of the second dielectric layer. A difference between the first and second width is in a range from about 3 um to about 6 um. The redistribution layer extends from the top surface of the second dielectric layer to the conductive pad. The third width is gradually decreased from the top surface to the bottom surface of the second dielectric layer.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

A method of forming a semiconductor structure includes following steps. The first substrate is etched to form an opening, such that a first conductive pad of the first substrate is exposed through the opening. A first RDL pad is formed over the first conductive pad and extends to a top surface of the first substrate. A first bond pad is formed on a first portion of the first RDL pad, in which the first portion of the first RDL pad overlaps with the top surface of the first substrate.

Embodiments of molded packages and corresponding methods of manufacture are provided. In an embodiment of a molded package, the molded package includes a laser-activatable mold compound having a plurality of laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the laser-activatable mold compound. A semiconductor die embedded in the laser-activatable mold compound has a plurality of die pads. An interconnect electrically connects the plurality of die pads of the semiconductor die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound.

The semiconductor device according to the present invention comprises; a semiconductor element having one surface with a plurality of electrode pads; an electrode structure including a plurality of metal terminals and a sealing resin. The plurality of metal terminals being disposed in a region along a circumference of the one surface. The sealing resin holding the plurality of metal terminals and being disposed on the one surface of the semiconductor element. The electrode structure includes a first surface opposed to the one surface of the semiconductor element, a second surface positioned in an opposite side of the first surface, and a third surface positioned between the first surface and the second surface. Each of the plurality of metal terminals is exposed from the sealing resin in at least a part of the second surface and at least a part of the third surface.