A semiconductor device includes a semiconductor layer that has a main surface, a main surface electrode that is arranged at the main surface, an insulating film that partially covers the main surface electrode such as to expose a portion of the main surface electrode, a mold layer that covers the insulating film such as to expose the main surface electrode, and a pad electrode that is arranged on the main surface electrode such as to be electrically connected to the main surface electrode.

An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.

This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

A semiconductor device includes: a semiconductor substrate with a first conductivity type; a semiconductor layer with a second conductivity type formed on the semiconductor substrate; a drain region with the second conductivity type and a source region with the second conductivity type formed to be spaced apart from each other in a surface region of the semiconductor layer; a drain buffer region with the second conductivity type formed in the semiconductor substrate directly under the drain region and in the semiconductor layer; a conductivity type well region with the second conductivity type formed on the semiconductor layer between the drain region and the drain buffer region; and a drain metal formed on the drain region to be electrically connected to the drain region and to overlap the well region in a plan view.

A semiconductor device includes a conductive support member, a control element, an insulating element, a driver element and a sealing resin. The conductive support member includes a first lead and a second lead. The first lead has a first pad portion. The second lead has a second pad portion. The second pad portion is adjacent to the first pad portion in a first direction perpendicular to a thickness direction of the first pad portion. The control element is mounted on the first pad portion. The insulating element is mounted on the first pad portion and electrically connected to the control element. The driver element is mounted on the second pad portion and electrically connected to the insulating element. The sealing resin covers the first pad portion, the second pad portion, the control element, the insulating element and the driver element. As viewed in the thickness direction, the first pad portion has a first edge adjacent to the second pad portion in the first direction and extending in a second direction perpendicular to the thickness direction and the first direction. The first edge has a first end and a second end opposite in the second direction. As viewed in the thickness direction, the second pad portion has a second edge adjacent to the first edge in the first direction and extending in the second direction. The second edge has a third end and a fourth end opposite in the second direction. One of the third end and the fourth end is located between the first end and the second end in the second direction.

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer.

A pad structure with a contact via array for high bond structure is provided. In some embodiments, a semiconductor substrate comprises a pad opening. An interconnect structure is under the semiconductor substrate, and comprises an interlayer dielectric (ILD) layer, a wiring layer, and the contact via array. The wiring layer and the contact via array are in the ILD layer. Further, the contact via array borders the wiring layer and is between the wiring layer and the semiconductor substrate. A pad covers the contact via array in the pad opening, and protrudes into the ILD layer to contact the wiring layer on opposite sides of the contact via array. A method for manufacturing the pad structure, as well as an image sensor with the pad structure, are also provided.

A semiconductor device manufacturing method which improves working efficiency. The method includes the step of transporting by air a package as a sealed moisture-proof bag which contains a case housing a semiconductor wafer laminate, in which the semiconductor wafer laminate has a plurality of semiconductor wafers stacked with a protective sheet interposed between semiconductor wafers. In order to facilitate separation of the protective sheet from the semiconductor wafers after unpacking the package, the protective sheet has a plurality of convex parts, a plurality of concave parts, and a flat part between a convex part and a concave part. A hole penetrating the protective sheet is made in each convex part and the center of the hole is located off the apex of the convex part.