A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

In a semiconductor device manufacturing method, a stacked substrate is formed. In the stacked substrate, a substrate is stacked repeatedly multiple times. The substrate includes a plurality of chip regions. In the semiconductor device manufacturing method, the stacked substrate is cut in a stacking direction among the plurality of chip regions, to separate the stacked substrate into a plurality of stacked bodies. In forming the stacked substrate, a first main surface of a first substrate and a second main surface of a second substrate are bonded to each other. In forming the stacked substrate, in a state where the second main surface is bonded to the first main surface, a third main surface of the second substrate opposite to the second main surface is thinned. In forming the stacked substrate, the third main surface of the second substrate and a fourth main surface of a third substrate are bonded to each other. In forming the stacked substrate, in a state where the fourth main surface is bonded to the third main surface, a fifth main surface of the third substrate opposite to the fourth main surface is thinned.

In a semiconductor device manufacturing method, a stacked substrate is formed. In the stacked substrate, a substrate is stacked repeatedly multiple times. The substrate includes a plurality of chip regions. In the semiconductor device manufacturing method, the stacked substrate is cut in a stacking direction among the plurality of chip regions, to separate the stacked substrate into a plurality of stacked bodies. In forming the stacked substrate, a first main surface of a first substrate and a second main surface of a second substrate are bonded to each other. In forming the stacked substrate, in a state where the second main surface is bonded to the first main surface, a third main surface of the second substrate opposite to the second main surface is thinned. In forming the stacked substrate, the third main surface of the second substrate and a fourth main surface of a third substrate are bonded to each other. In forming the stacked substrate, in a state where the fourth main surface is bonded to the third main surface, a fifth main surface of the third substrate opposite to the fourth main surface is thinned.

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.