An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

An aspect of the present invention provides a metal pillar in a columnar shape formed by cutting a metal wire to a predetermined length. The metal pillar has a burr length of 0.1 to 0.5 ?m on the cutting surface and provide a connecting pillar that has a solder layer on at least one area of the outer surface of the metal pillar, which comprises Sn, Cu, and Ag.

The present invention discloses a package structure for reducing warpage of plastic package wafer, including an adapter board, a chip mounted on the adapter board, and a first plastic package layer covering the chip, through-silicon-vias are disposed on the adapter board, the first and second surfaces of the adapter board are respectively provided with external connection solder balls and/or external connection solder pads electrically connected with the through-silicon-vias. The process of manufacturing the package structure includes: after the first surface process of the adapter board is completed, bonding the first carrier on its first surface, then cutting the first carrier to expose the chip-mounting area, and then carrying out subsequent processes such as chip mounting, and finally cutting and removing the first carrier to complete the package.

A system and method are provided for depositing a substance onto a substrate, the system comprising: a chamber adapted to operate under high vacuum; an apparatus for receiving and cleaning the substrate to produce a clean substrate and for delivering the clean substrate to a coating position in the chamber under high vacuum; a carrier assembly for receiving the clean substrate from the apparatus and for retaining the substrate at the coating position; an evaporator adapted to hold a supply of the substance in the chamber and to evaporate and produce a discharge of the substance; and a collimator disposed within the chamber between the supply of the substance and the carrier assembly, the collimator being configured to define an aperture proximal to the substrate and to capture the discharge but for that which is directed through the aperture.

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.

Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having a plated film formed in the inner surface. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are selectively present at a position where the through holes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through holes are connected by the conductive particles, and the semiconductor substrates each having the through hole are bonded by an insulating adhesive.

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

A semiconductor fabrication apparatus has a transfer plate having a plurality of transfer pins to transfer a flux onto a plurality of lands on a semiconductor substrate, a holder movable with the transfer plate, to hold the transfer plate, a positioning mechanism to perform positioning of the holder so that the plurality of lands and the respective transfer pins contact each other; and a pitch adjuster to adjust a pitch of at least part of the plurality of transfer pins.