H01L2224/114

STT-MRAM FLIP-CHIP MAGNETIC SHIELDING AND METHOD FOR PRODUCING THE SAME

Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

STT-MRAM FLIP-CHIP MAGNETIC SHIELDING AND METHOD FOR PRODUCING THE SAME

Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

STT-MRAM flip-chip magnetic shielding and method for producing the same

Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

STT-MRAM flip-chip magnetic shielding and method for producing the same

Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

Tooling for coupling multiple electronic chips
10340239 · 2019-07-02 · ·

A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.

Interconnect crack arrestor structure and methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

Interconnect crack arrestor structure and methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

MULTIPLE SIZED BUMP BONDS
20190198474 · 2019-06-27 ·

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

MULTIPLE SIZED BUMP BONDS
20190198474 · 2019-06-27 ·

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

Fingerprint sensor and manufacturing method thereof

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.