Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip side surface. A first conductive bulk is formed embedded in the molding compound. The first conductive bulk has a first number of first chip-side bond pad surfaces and a second number of first solder ball-side surfaces exposed from the chip side surface and the ball-side surface, respectively. The width of the first conductive bulk is greater than the first width of the first chip-side bond pad surfaces and the second width of the first solder ball-side surfaces.

The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including Al.sub.xGa.sub.(1-x)N (0<x<1) and a quantum well layer including Al.sub.yGa.sub.(1-y)N (0<x<y<1), and at least one of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer includes AlGaN. The intermediate layer includes AlN and has a plurality of air voids formed in the AlN. At least some of the air voids are irregularly aligned and the number of the air voids is 10.sup.7 to 10.sup.10/cm.sup.2.

An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

A semiconductor light emitting device includes a substrate formed of a first material; and a convex portion protruding from the substrate and including: a first layer formed of the first material as that of the substrate; and a second layer formed of a second material different from the first material and disposed on the first layer. A second height of the second layer is greater than a first height of the first layer.

A self-emission type display including a carrier substrate, a light-emitting element, a first electrode, and a second electrode is provided. The light-emitting element is disposed on the carrier substrate and has a first pad and a second pad. The first electrode has a plurality of first stripe portions electrically connected to a first electric potential. The first pad of the light-emitting element is electrically connected to the carrier substrate through at least one first strip portion. The second electrode has a plurality of second stripe portions electrically connected to a second electric potential. The first electrode and the second electrode are separated from each other. The second pad of the light-emitting element is electrically connected to the carrier substrate through at least one second strip portion. The first electric potential is different from the second electric potential.

Embodiments provide a light emitting device module including a circuit board, a light emitting device bonded to a conductive layer on the circuit board via a conductive adhesive, a phosphor layer disposed on a side surface and an upper surface of the light emitting device, and a lens on the circuit board and the phosphor layer. A void is generated between the light emitting device and the circuit board.

The present invention relates to a light-emitting diode having enhanced liability. More particularly, a light-emitting diode has enhanced liability in a high-temperature and/or high humidity environment as well as in a room-temperature environment and can have decrease in light-emitting characteristics prevented. In addition, the present invention relates to a light-emitting diode comprising a structure which enables enhancing of light reflection and having enhanced light extraction efficiency by means of light reflection through the structure.

There is provided a nitride semiconductor ultraviolet light-emitting element capable of efficiently releasing a waste heat generated in an ultraviolet light emitting operation. The nitride semiconductor ultraviolet light-emitting element includes a semiconductor laminated portion 11 having an n-type AlGaN layer 6, an active layer 7 of an AlGaN layer, and p-type AlGaN layers 9 and 10; an n electrode 13; a p electrode 12; a protective insulating film 14, and a first plated electrode 15 formed by a wet plating method and composed of copper or alloy containing copper as a main component. The semiconductor laminated portion 11 is formed in a first region R1, and the p electrode is formed on the portion 11. An upper surface of the n-type AlGaN-based semiconductor layer 6 is exposed in a second region, and the n electrode 13 is formed on the upper surface. The protective insulating film 14 has openings for exposing at least one part of the n electrode 13 and at least one part of the p electrode 12. The first plated electrode 15 is spaced apart from the exposed surface of the n electrode 13 and covers a whole upper surface and a whole outer side surface of the first region R1, and a part of the second region R2 which is in contact with the first region R1.