Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the die-attach pad, or of the lead fingers proximate to a geometric center of the lead frame may be rounded to exhibit a radius of curvature of at least two times a greatest thickness of the die-attach pad, the thickness measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and a largest of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the die-attach pad, or of the lead fingers proximate to a geometric center of the lead frame may be rounded to exhibit a radius of curvature of at least two times a greatest thickness of the die-attach pad, the thickness measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and a largest of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.

A semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a plurality of hollow vias extending through the package substrate. The semiconductor die is electrically connected to the package substrate. The hollow vias are disposed under the semiconductor die.

A package structure is provided. The package structure includes a leadframe including a first portion and a second portion. The first portion includes a first base part and a plurality of first extended parts connected to the first base part. The second portion includes a second base part and a plurality of second extended parts connected to the second base part. The first extended parts and the second extended parts are arranged in such a way that they alternate with each other. In the package structure, a chip is disposed on a part of the first extended parts of the first portion and the second extended parts of the second portion of the leadframe.

Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.

A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.

Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

A semiconductor device includes: a first electrode provided on a semiconductor multilayer structure; a second electrode provided on a substrate; and a bonding metal layer which bonds the first electrode and the second electrode together. The bonding metal layer includes a gap inside.

An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.