Semiconductor packages are provided. In one example, a semiconductor package includes a submount. The semiconductor package further includes a semiconductor die on the submount. The submount defines a base plane, and the submount includes at least one stud protrusion extending from the base plane in a direction toward the semiconductor die.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

A power module includes an upper substrate, a lower substrate, a first semiconductor chip, a first spacer electrically interconnecting a first metal layer of the upper substrate and a second metal layer of the lower substrate, a second spacer electrically interconnecting the first semiconductor chip and the first metal layer, and a first connection layer configured to form a current path, and a power lead.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first dielectric material including first conductive pathways through the first dielectric material, the first dielectric material having a first surface and an opposing second surface, wherein the first surface includes conductive contacts having a first pitch between 170 microns and 400 microns; a first die, coupled to the second surface of the first dielectric material; a second dielectric material, on the first die, including second conductive pathways through the second dielectric material, the second dielectric material having a third surface and an opposing fourth surface; and a second die coupled to the fourth surface of the second dielectric material by interconnects having a second pitch between 18 microns and 150 microns.