A method of forming a bonding assembly that includes positioning a plurality of polymer spheres against an opal structure and placing a substrate against a second major surface of the opal structure. The opal structure includes the first major surface and the second major surface with a plurality of voids defined therebetween. The plurality of polymer spheres encapsulates a solder material disposed therein and contacts the first major surface of the opal structure. The method includes depositing a material within the voids of the opal structure and removing the opal structure to form an inverse opal structure between the first and second major surfaces. The method further includes removing the plurality of polymer spheres to expose the solder material encapsulated therein and placing a semiconductor device onto the inverse opal structure in contact with the solder material.

Methods for forming bonded assemblies using metal inverse opal and cap structures are disclosed. In one embodiment, a method for forming a bonded assembly includes positioning a substrate against a polymer support that is porous, depositing a metal onto and within the polymer support, disposing a cap layer to the polymer support opposite of the substrate to form a bottom electrode, and removing the polymer support from between the substrate and the cap layer to form a metal inverse opal structure disposed therebetween.

Methods for forming bonded assemblies using metal inverse opal and cap structures are disclosed. In one embodiment, a method for forming a bonded assembly includes positioning a substrate against a polymer support that is porous, depositing a metal onto and within the polymer support, disposing a cap layer to the polymer support opposite of the substrate to form a bottom electrode, and removing the polymer support from between the substrate and the cap layer to form a metal inverse opal structure disposed therebetween.

A chip packaging device is provided, which includes a main body unit, packaging unit and an aligning unit. The main body unit includes a mounting base, holder and a rotational platform. The packaging unit includes upper and lower bonding elements, upper and lower chips and a mask; a vertical axis is at the middle of the upper and the lower bonding elements, and a horizontal axis is above the lower bonding element. The aligning unit includes an aligning detector and a first focusing detector. When the lower chip and the mask are disposed on the lower bonding element, place the liquid sample in the mask and spread a packaging adhesive over the surface thereof; then, remove the mask and use the aligning detector and the first focusing detector to detect the position of the lower chip respectively, such that the chips can be aligned and bonded with each other.

A chip packaging device is provided, which includes a main body unit, packaging unit and an aligning unit. The main body unit includes a mounting base, holder and a rotational platform. The packaging unit includes upper and lower bonding elements, upper and lower chips and a mask; a vertical axis is at the middle of the upper and the lower bonding elements, and a horizontal axis is above the lower bonding element. The aligning unit includes an aligning detector and a first focusing detector. When the lower chip and the mask are disposed on the lower bonding element, place the liquid sample in the mask and spread a packaging adhesive over the surface thereof; then, remove the mask and use the aligning detector and the first focusing detector to detect the position of the lower chip respectively, such that the chips can be aligned and bonded with each other.

In a manufacturing method of a semiconductor device including a substrate having a front surface and a rear surface, and a film attached to the rear surface, the film is attached on the rear surface, a rear surface side groove is provided by half-cutting the substrate from the rear surface together with the film, a protective member is attached to the film after the rear surface side groove is provided, and a front surface side groove connected to the rear surface side groove is provided by dicing the substrate from the front surface after the protective member is attached.

A carbon nanotube structure includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. And a heat dissipation sheet includes a plurality of carbon nanotube structures arranged in a sheet form, wherein each of the carbon nanotube structures includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes.

A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.

A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure.