A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. The circuit layer includes a central region and a peripheral region electrically connected to the central region. A chip is disposed on the central region of the circuit layer. The chip includes an active surface at a distance from the circuit layer and a sensing area on the active surface. An encapsulant is formed on the circuit layer to encapsulate the chip and the conductive connectors. A redistribution layer is formed on the encapsulant to electrically connect the chip and the conductive connectors. The redistribution layer partially covers the chip and includes a window corresponding to the sensing area of the chip. A package structure is also provided.

A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. The circuit layer includes a central region and a peripheral region electrically connected to the central region. A chip is disposed on the central region of the circuit layer. The chip includes an active surface at a distance from the circuit layer and a sensing area on the active surface. An encapsulant is formed on the circuit layer to encapsulate the chip and the conductive connectors. A redistribution layer is formed on the encapsulant to electrically connect the chip and the conductive connectors. The redistribution layer partially covers the chip and includes a window corresponding to the sensing area of the chip. A package structure is also provided.

A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.

A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.

A semiconductor device includes a semiconductor element having an NiV electrode and a conductor, the semiconductor element and the conductor being bonded via Sn-based lead-free solder. In the semiconductor device, an SnV compound layer and an (Ni, Cu)3Sn4 compound layer adjacent to the SnV compound are formed adjacent to an interface between the semiconductor element and the Sn-based lead-free solder. A manufacturing method for a semiconductor device according to the present invention includes: causing the Sn-based lead-free solder and the NiV electrode to react with each other to form an SnV layer and an (Ni, Cu)3Sn4 compound layer; and following formation of the SnV layer, leaving an unreacted layer of the NiV electrode, the unreacted layer having not reacted with the Sn-based lead-free solder, intact.

A method for bonding of a first solid substrate to a second solid substrate which contains a first material with the following steps, especially the following sequence: formation or application of a function layer which contains a second material to the second solid substrate, making contact of the first solid substrate with the second solid substrate on the function layer, pressing together the solid substrates for forming a permanent bond between the first and second solid substrate, at least partially reinforced by solid diffusion and/or phase transformation of the first material with the second material, an increase of volume on the function layer being caused.

A method for assembling a first substrate and a second substrate via metal adhesion layers, the method including: depositing, on a surface of each of the first and second substrates, a metal layer with a thickness controlled to limit surface roughness of each of the deposited metal layers to below a roughness threshold; exposing the metal layers deposited on the surface of the first and second substrates to air; directly adhering the first and second substrates by placing the deposited metal adhesion layers in contact, the surface roughness of the contacted layers being that obtained at an end of the depositing. The adhesion can be carried out in the air, at atmospheric pressure and at room temperature, without applying pressure to the assembly of the first and second substrates resulting from directly contacting the deposited metal adhesion layers.

A wafer bonding method includes providing a first wafer including a first wafer surface, forming a first metal layer on the first wafer surface, and forming a first annular retaining wall structure including a first annular retaining wall and a second annular retaining wall surrounded by the first annular retaining wall. The first metal layer is formed between the first annular retaining wall and the second annular retaining wall. The method includes providing a second wafer including a second wafer surface, forming a second metal layer on the second wafer surface, and forming a second annular retaining wall structure including a third annular retaining wall and a fourth annular retaining wall surrounded by the third annular retaining wall. The second metal layer is formed between the third annular retaining wall and the fourth annular retaining wall. The method further includes bonding the first metal layer to the second metal layer.

A manufacturing method for a package device includes a chip preparation step of preparing a device chip that includes an adhesive layer, a mounting substrate preparation step of preparing a mounting substrate that has a chip adhesion region to which the device chip is to be adhered, an electrode portion to be connected to the device chip, and a stepped portion formed between the chip adhesion region and the electrode portion, a mounting step of adhering the device chip to the chip adhesion region of the mounting substrate, a hardening step of hardening the adhesive layer, a connection step of electrically connecting the device chip and the electrode portion by a wire, and a molding step of covering the device chip and the wire with mold resin.

A manufacturing method for a package device includes a chip preparation step of preparing a device chip that includes an adhesive layer, a mounting substrate preparation step of preparing a mounting substrate that has a chip adhesion region to which the device chip is to be adhered, an electrode portion to be connected to the device chip, and a stepped portion formed between the chip adhesion region and the electrode portion, a mounting step of adhering the device chip to the chip adhesion region of the mounting substrate, a hardening step of hardening the adhesive layer, a connection step of electrically connecting the device chip and the electrode portion by a wire, and a molding step of covering the device chip and the wire with mold resin.