Patent classifications
H01L2224/29
Semiconductor package
A semiconductor package includes: a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface opposite to the active surface; a heat-dissipating member disposed on the inactive surface of the semiconductor chip and including graphite; an encapsulant sealing at least a portion of each of the semiconductor chip and the heat-dissipating member; a capping metal layer disposed directly between the heat-dissipating member and the encapsulant; and a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the heat-dissipating member includes holes passing through at least a portion of the heat-dissipating member, and the holes overlap the inactive surface of the semiconductor chip.
Integrated electronic device with transceiving antenna and magnetic interconnection
An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.
Burned-in Component Assembly
A component support fixture having a plurality of oversized compartments of the same size mounted on a top surface of an anisotropic adhesive film such that each of a plurality of burned-in components of different heights and widths are accommodated within a compartment. Patterned traces are formed on the bottom surface of the anisotropic film. The leads of the burned-in components are in electrically communication with those traces through the anisotropic film.
USE OF NICKEL AND NICKEL-CONTAINING ALLOYS AS CONDUCTIVE FILLERS IN ADHESIVE FORMULATIONS
In accordance with the present invention, there are provided novel conductive adhesives and methods for the preparation thereof. In another aspect, the present invention provides novel conductive inks and methods for the preparation thereof. In yet another aspect, the present invention provides novel die attach films and methods for the preparation thereof. In still another aspect, the present invention provides novel die attach pastes and methods for the preparation thereof.
Mixed alloy solder paste
A solder paste consists of an amount of a first solder alloy powder between 60 wt % to 92 wt %; an amount of a second solder alloy powder greater than 0 wt % and less than 12 wt %; and a flux; wherein the first solder alloy powder comprises a first solder alloy that has a solidus temperature above 260 C.; and wherein the second solder alloy powder comprises a second solder alloy that has a solidus temperature that is less than 250 C.
Method for permanent connection of two metal surfaces
A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.
Chip-middle type fan-out panel-level package and packaging method thereof
A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.
Semiconductor device including a connection unit and semiconductor device fabrication method of the same
A semiconductor device includes a plurality of semiconductor units each including a laminated substrate formed by laminating an insulating board and a circuit board and a semiconductor element joined to the circuit board using a joining material which irreversibly makes a phase transition into a solid-phase state. In addition, the semiconductor device may include a base plate to which each of the plurality of semiconductor units is joined using solder and a connection unit which electrically connects the plurality of semiconductor units in parallel.
CONDUCTIVE PARTICLE, ITS MANUFACTURING METHOD AND ANISOTROPIC CONDUCTIVE ADHESIVE
The present disclosure provides a conductive particle, its manufacturing method and the anisotropic conductive adhesive. The conductive particle comprises a rigid inner core, a resin layer covering an outer surface of the rigid inner core, and a conductive layer covering an outer surface of the resin layer.
Bonding structure and method
A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.