A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.

A semiconductor device includes a semiconductor element having a front electrode, an electrode plate having an area larger than the front electrode of the semiconductor element in a two-dimensional view and made of aluminum or aluminum alloy, and a metal member having a joint surface joined to the front electrode of the semiconductor element with solder, having an area smaller than the front electrode of the semiconductor element in a two-dimensional view, made of a metal different from the electrode plate, and fastened to the electrode plate to electrically connect the front electrode of the semiconductor element to the electrode plate.

An electrical power conversion device is provided which includes a stack of semiconductor modules and a plurality of cooling pipes. Each of the cooling pipes includes a first and a second outer shell plate which are electrically conductive. Each of the outer shell plates includes a flow-path defining portion which defines a coolant flow path between the outer shell plates and a flow-path outer periphery forming a circumference of the flow-path defining portion. The flow-path outer periphery of at least one of the outer shell plates has formed thereon an outer shell protrusion which is laid to overlap power terminals or control terminals extending from the semiconductor module to cancel a magnetic flux, as developed around the power terminals or the control terminals, thereby decreasing the inductance of the power terminals or the control terminals.

A power semiconductor device having a high degree of reliability even when an operable temperature of a power semiconductor element is sufficiently increased. The power semiconductor device includes: a power semiconductor element including an electrode formed on a first surface; a first stress mitigation portion connected to the electrode with a first bonding portion being interposed; and a wiring portion electrically connected to the first stress mitigation portion with a second bonding portion being interposed. A bonding strength of the first bonding portion is higher than a bonding strength of the second bonding portion.

The module (PM1) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (IT.sub.HS, ID.sub.HS; IT.sub.HS, ID.sub.HS) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one.

A power conversion apparatus is provided in which an upper arm semiconductor device, a lower arm semiconductor device and a capacitor. At least either upper arm semiconductor device or lower arm semiconductor device constitutes a parallel-connected body. In an opposite arm against the parallel-connected body, a permissible element is provided. In the switching elements that constitute the parallel-connected body, a last off element and a non-last off circuit are identified. Inductance of a last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor is smaller than inductance of a non-last off closed circuit where current flows through the last off element, reflux element in the opposite arm and the capacitor.

An electronic device includes an electronic component, a sealing resin body, and a plurality of conductive members electrically connected to the electronic component in the sealing resin body, including respective portions exposed from the sealing resin body to the outside of the sealing resin body, and having different potentials. The conductive members include a heat sink and a terminal extending from an inside to the outside of the sealing resin body. A surface of the terminal includes, as a part covered with the sealing resin body, a higher adhesion part and a lower adhesion part. The lower adhesion part is provided in an entire portion of a back surface of the terminal, the back surface being opposite to a connection surface of the terminal which is adjacent to a connection part electrically connected to the electronic component. The higher adhesion part is provided in the connection surface.

Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

The invention discloses a parallel electrode combination, which includes a first power module electrode and a second power module electrode, wherein a soldering portion of the first power module electrode and a soldering portion of the second power module electrode are respectively used to connect a copper layer of a power source inside a power module, and a connecting portion of the first power module electrode and a connecting portion of the second power module electrode are opposite in parallel. The invention further discloses a power module and a power module group using the parallel electrode combination. In the invention, the connecting portion of the first power module electrode and the connecting portion of the second power module electrode are opposite in parallel.

A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.