Various embodiments include a semiconductor component comprising: a first carrier part; a second carrier part arranged opposite the first carrier part; a semiconductor element arranged between the first carrier part and the second carrier part; a contact surface arranged on one of the parts; a contact sleeve arranged on one of the carrier parts opposite the contact surface; and a contact pin with, at one axial end, an end face providing an electrical contact connection of the contact surface and, in a region averted from said axial end, a connection region for the connection of the contact pin with the contact sleeve by means of press fitting. At least one of the first carrier part or the second carrier part comprises a printed conductor connected to the contact surface and/or to the contact sleeve.

A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 m or more.

A semiconductor device may include: a first and a second semiconductor elements; and a first and a second insulated substrates each including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, the metal layers respectively on one face of the first and the second insulated substrate being connected to the first and the second semiconductor element, wherein the metal layers respectively on the one face of the first and the second insulated substrate are electrically connected via a joint each other; the joint is constituted of a separate member from the insulated substrates; and one end of the joint is connected to the metal layer on the one face of the first insulated substrate, and another end of the joint is connected to the metal layer on the one face of the second insulated substrate.

The module (PM1) has an architecture with 3D stacking of the electronic power switching chips (IT, ID) and comprises first and second dielectric substrates (SH, SL) that are intended to come into thermal contact with first and second heat sinks (DH, DL), respectively, at least one pair of first and second stacked electronic power switching chips (IT.sub.HS, ID.sub.HS; IT.sub.HS, ID.sub.HS) and a common intermediate substrate (SC), the first and second electronic power switching chips being sandwiched between the first dielectric substrate and the common intermediate substrate and between the common intermediate substrate and the second dielectric substrate, respectively. According to the invention, the common intermediate substrate is a metal element formed as a single piece and comprises a central portion for the implantation of the electronic power switching chips and at least one thermal conduction portion that is in thermal contact with the first dielectric substrate and/or the second dielectric substrate.

A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.

Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 m to 0.8 m, and flake-shaped micro copper particles having a maximum particle size of 1 m to 20 m, and an aspect ratio of 4 or greater, and the amount of the micro copper particles contained, which are included in the metal particles and have a maximum particle size of 1 m to 20 m and an aspect ratio of less than 2, is 50% by mass or less on the basis of a total amount of the flake-shaped micro copper particles.

Disclosed is a power module capable of maximizing heat dissipation performance through application of a thick lead frame and a ceramic coating layer to upper and lower sides of a semiconductor device.

Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin.

A semiconductor device includes: at least one power semiconductor element; a sealing resin disposed so as to seal the power semiconductor element; and a plurality of electrical terminals each electrically connected to the power semiconductor element and each including a protrusion protruding from a surface of the sealing resin. The protrusion includes a first part that is provided on a side of the sealing resin in a protrusion direction of the protrusion and of which a cross-section intersecting the protrusion direction has one of a circular shape and an oval shape.