An integrated circuit (IC) package includes a lead frame and a first die attached to the lead frame. The IC package also includes a first clip attached to first die and the lead frame. The IC package further includes a second die attached to first clip and the lead frame. The IC package still further includes a second clip with a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending to and contacting a side of the second die via a layer of solder paste. The second clip includes a sawn or lased edge at a second side of the second clip opposing the first side of the second clip.

A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar.

A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.

A semiconductor device includes a conductive member including first, second and third conductors mutually spaced, a first semiconductor element having a first obverse surface provided with a first drain electrode, a first source electrode and a first gate electrode, and a second semiconductor element having a second obverse surface provided with a second drain electrode, a second source electrode and a second gate electrode. The first conductor is electrically connected to the first source electrode and the second drain electrode. The second conductor is electrically connected to the second source electrode. As viewed in a first direction crossing the first obverse surface, the second conductor is adjacent to the first conductor in a second direction crossing the first direction. The third conductor is electrically connected to the first drain electrode and is adjacent to the first conductor and the second conductor as viewed in the first direction.

A method for forming packaged electronic devices includes providing a substrate having pads connected by conductive pad linking portions and semiconductor devices attached to the pads in different orientations. A second substrate is provided having conductive connectors each with a plate portion, a conductive member extending from a side segment of the plate portion, and a connective portion extending from the conductive member distal to the plate portion. The second substrate further has conductive linking portions physically connecting adjoining plate portions together. Each plate portion is attached to one of the semiconductor devices to provide a subassembly The conductive linking portions are configured to maintain the adjoining plate portions in substantial alignment with the semiconductor devices and to maintain the connective portions is a desired alignment during the plate portion attachment step. A package body is provided to encapsulate the subassembly where bottom surfaces of each connective portion is exposed outside of a major surface of the package body. The method includes separating the encapsulated subassembly to provide the packaged electronic devices such that the separating step severs the conductive linking portions.

A transistor configured for higher power can be constructed using multiple transistor dies coupled in parallel. This approach of distributing power and heat over multiple transistor dies can allow each transistor die to be made smaller, which can be helpful in improving yield. This is especially true for emerging technologies, such as silicon carbide (SiC). Power modules for power conversion may require a plurality of these multi-die transistors in a package. A package that accommodates the numerous connections required for a multi-die power module is disclosed. The package utilizes a lead frame to provide a three-dimensional sandwich structure in which multiple dies are positioned between two direct bonded copper (DBC) substrates.

A packaged semiconductor device has a die attach pad and leads disposed proximate to the die attach pad. Each lead has a lead bottom surface and a lead end surface. A semiconductor device attached adjacent to a top surface of the die attach pad, and a conductive clip is attached to the semiconductor device and at least one of the leads. The conductive clip comprises a first tie bar extending from a first side surface of the conductive clip. A package body encapsulates the semiconductor device, the conductive clip, portions of the leads, at least a portion of the first tie bar, and at least a portion of the die attach pad. Each lead end surface is exposed in a side surface of the package body, and an end surface of the first tie bar is exposed in a first side surface of the package body. A conductive layer is disposed on each lead end surface but is not disposed on the end surface of the first tie bar.

A method for forming packaged semiconductor devices comprises providing a first conductive frame structure. The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first sub-assembly, wherein the second conductive frame structure comprises a plurality of interconnected conductive connective structures. The method includes encapsulating the first sub-assembly with an encapsulating layer to provide an encapsulated sub-assembly. The method includes removing joined conductive portions of the first conductive frame structure to form a plurality of conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly. The method includes forming a conductive layer on the conductive flank surfaces. The method includes separating the encapsulated sub-assembly to provide the packaged semiconductor devices each having portions of the conductive flank surfaces covered by the conductive layer.

A method for forming packaged semiconductor devices comprises providing a first conductive frame structure. The method includes coupling a second conductive frame structure to the first conductive frame structure to provide a first sub-assembly, wherein the second conductive frame structure comprises a plurality of interconnected conductive connective structures. The method includes encapsulating the first sub-assembly with an encapsulating layer to provide an encapsulated sub-assembly. The method includes removing joined conductive portions of the first conductive frame structure to form a plurality of conductive flank surfaces disposed on side surfaces of the encapsulated sub-assembly. The method includes forming a conductive layer on the conductive flank surfaces. The method includes separating the encapsulated sub-assembly to provide the packaged semiconductor devices each having portions of the conductive flank surfaces covered by the conductive layer.