A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A package structure is provided. The package structure includes a wiring structure, a first element, and a plurality of first wires. The wiring structure has a first recess recessed from a first surface of the wiring structure. The first element is disposed over the first surface of the wiring structure. The first wires are disposed in the first recess and extending in a direction from the wiring structure to the first element. The first wires are configured to reduce an inclination of the first element with respect to the first surface of the wiring structure.

A method of manufacturing a bond wire having a metal core, a dielectric layer, and a ground connectable metallization, wherein the bond wire has one or more vapor barrier coatings, and manufacturing a die package with at least one bond wire according to the invention.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A package structure includes a wiring structure, a first electronic device and a reinforcement structure. The first electronic device is disposed over the top surface of the wiring structure, and has a bottom surface facing the top surface of the wiring structure. The first electronic device includes a plurality of first wires. The reinforcement structure is disposed over the top surface of the wiring structure, and includes a plurality of second wires directly contacting the plurality of first wires to reduce a variation of an elevation of the bottom surface of the first electronic device with respect to the top surface of the wiring structure.

A bond wire having a metal core, a dielectric layer, and a ground connectable metallization, wherein the bond wire has one or more vapor barrier coatings. Further, the present invention relates to a die package with at least one bond wire according to the invention.

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

A semiconductor device includes a base, one or a plurality of chips that include a semiconductor chip provided on the base, a first bonding wire connected to at least one of the one or the plurality of chips, a second bonding wire that extends in a direction intersecting with an extending direction of the first bonding wire when viewed from a thickness direction of the base, and a resin layer that is provided on the base and seals the one or the plurality of chips, the first bonding wire and the second bonding wire. The first bonding wire and the second bonding wire are not in contact with each other, and the first bonding wire is contactable with the second bonding wire when the first bonding wire is inclined toward the second bonding wire.

A method includes providing a plurality of semiconductor devices on a semiconductor structure, providing a top side metallization on a first side of the semiconductor structure, wherein the top side metallization comprises a plurality of bond pads on each of the semiconductor devices, and providing a back side metallization on a second side of the semiconductor structure opposite the first side of the semiconductor structure. The back side metallization is not provided on portions of the second side of the semiconductor structure corresponding to dicing streets between the semiconductor devices.