A semiconductor package includes a package substrate, a semiconductor device, an antenna substrate and a package body. The semiconductor device is disposed on an upper surface of the package substrate. The antenna substrate is disposed on the semiconductor device and includes a core layer, a grounding layer formed on a lower surface of the core layer, and an antenna layer formed on an upper surface of the core layer and electrically connected to the grounding layer through a conductive via of the core layer. The package body encapsulates the semiconductor device and the antenna substrate.

A ceramic substrate is provided, including: a board having a first surface and a second surface opposing the first surface; first electrical contact pads disposed on the first surface; second electrical contact pads disposed on the second surface; conductive pillars disposed in the board and connecting the first surface and the second surface to electrically connect the electrical contact pad and the second electrical contact pad; a first heat conductive pad disposed on the first surface; a second heat conductive pad disposed on the second surface; and a heat conductive pillar disposed in the board and connecting the first surface and the second surface to contact and be coupled with the first heat conductive pad and the second heat conductive pad, wherein the heat conductive pillar has a width greater than or equal to widths of the conductive pillars and greater than or equal to 300 micrometers.

Disclosed is a semiconductor package comprising a package substrate having a mount region and a peripheral region that surrounds the mount region, a semiconductor device on the mount region of the package substrate, a package cap on the peripheral region of the package substrate and including a partition portion that surrounds the semiconductor device and an extension portion that covers the semiconductor device, and an adhesive layer between the package substrate and a bottom surface of the package cap. The bottom surface of the package cap has a trench. The trench has a trapezoidal cross-section whose width decreases in a direction receding from the bottom surface of the package cap. The adhesive layer is in contact with a top surface of the package substrate and the bottom surface of the package cap. The adhesive layer fills the trench.

An electronic device includes a carrier substrate, a first electronic chip and a second chip. The first chip is mounted on the carrier substrate via interposed electrical connection elements electrically connecting a front electrical connection network of the first chip and an electrical connection network of the carrier substrate. The second chip is mounted on the first chip via interposed electrical connection elements electrically connecting a front electrical connection network of the second chip and a back electrical connection network of the first chip Electrical connection wires electrically connect the back electrical connection network of the first chip to the electrical connection network of the carrier substrate.

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

A microelectromechanical sensor module includes a sensing mechanism for measuring an acceleration, pressure, air humidity or the like, a control mechanism for controlling the sensing mechanism, an energy supply mechanism for supplying the sensor module with energy, and a transmission mechanism for transmitting signals of the sensing mechanism. At least three of the mechanisms are integrated at the chip level in at least one chip in each case. A corresponding method is implemented to produce the microelectromechanical sensor module.

A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided.

A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

An integrated circuit (IC) that includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the front side surface. An inductive structure is located within a deep trench formed in the circuit substrate below the backside surface. The inductive structure is coupled to the active circuitry.