A unit lead frame includes a periphery structure, a die paddle inside of the periphery structure, a plurality of leads extending between the periphery structure and the die paddle, and trenches or grooves extending from an outer surface of the periphery structure and configured to guide liquefied molding material onto the periphery structure along sidewalls of the trenches or grooves.

Provided are a semiconductor module capable of further increasing an effect of canceling out a parasitic inductance by a current and a power converter including the semiconductor module. The semiconductor module includes a first leadframe, a second leadframe, a third leadframe, an insulating material, a first semiconductor element, and a second semiconductor element. The first leadframe is a plate-shaped wiring path to which a first potential is applied. The second leadframe is a plate-shaped wiring path including an output terminal. The third leadframe is a plate-shaped wiring path to which a second potential is applied. The first semiconductor element is directly joined to the first leadframe with a joint material therebetween, and the second semiconductor element is directly joined to the second leadframe with a joint material therebetween. The first leadframe and the second leadframe face each other with the insulating material therebetween.

Provided are a semiconductor module capable of further increasing an effect of canceling out a parasitic inductance by a current and a power converter including the semiconductor module. The semiconductor module includes a first leadframe, a second leadframe, a third leadframe, an insulating material, a first semiconductor element, and a second semiconductor element. The first leadframe is a plate-shaped wiring path to which a first potential is applied. The second leadframe is a plate-shaped wiring path including an output terminal. The third leadframe is a plate-shaped wiring path to which a second potential is applied. The first semiconductor element is directly joined to the first leadframe with a joint material therebetween, and the second semiconductor element is directly joined to the second leadframe with a joint material therebetween. The first leadframe and the second leadframe face each other with the insulating material therebetween.

A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip

A power electronics method and assembly produced by the method. The assembly has a substrate, having a power semiconductor element, and an adhesion layer disposed therebetween, wherein the substrate has a first surface that faces a power semiconductor element, a power semiconductor element has a third surface that faces the substrate, the adhesion layer has a second surface which, preferably across the full area, contacts the third surface and has a first consistent surface contour having a first roughness, and wherein a fourth surface of the power semiconductor element that is opposite the third surface has a second surface contour having a second roughness, said second surface contour following the first surface contour.

A pressing ram having an elastic cushion element and intended for the material-bonded press-sintering connection of a first connection partner to a second connection partner of a power-electronics component. The elastic cushion element of the pressing ram is enclosed by a dimensionally stable frame, within which the cushion element and a guide part of the pressing ram are guided for linear movement such that the dimensionally stable frame lowers onto the first connection partner, or a workpiece carrier with the first connection partner arranged therein, and, following abutment against the same, the pressing ram together with the elastic cushion element is lowered onto the second connection partner and the elastic cushion exerts a pressure necessary for connecting the first connection partner to the second connection partner.

A unit lead frame includes a periphery structure, a die paddle inside of the periphery structure, a plurality of leads extending between the periphery structure and the die paddle, and trenches or grooves extending from an outer surface of the periphery structure and configured to guide liquefied molding material onto the periphery structure along sidewalls of the trenches or grooves.

A semiconductor device packaging assembly includes a lead frame strip having a plurality of unit lead frames. Each of the unit lead frames includes a periphery structure connected to adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads extending between the periphery structure and the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material onto the periphery structure.

A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other.

A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.