A compound and method of use thereof consisting of an A-staged thermoplastic-polyimide (TPI) adhesive, a viscous uncured liquid of polyamic-acid polymer (PAA), the TPI precursor, synthesized and dissolved in a polar aprotic organic solvent, and including, as appropriate, combinations of particulate ceramic and/or metallic thermally conducting, electrically insulating, and thermally conducting, electrically conducting fillers for interface-bonding to create a robust joint between surfaces with conventional lamination processes that utilize relatively moderate temperatures and applied pressures.

Provided is an electronic component mounting method including the steps of: placing an electronic component having a primary surface on which a first electrode is formed, on a circuit member having a primary surface on which a second electrode corresponding to the first electrode is formed, with solder and a bonding material including a thermosetting resin interposed between the first and second electrodes; subjecting the thermosetting resin to a first heating at a temperature lower than the melting point of the solder and thus causing the resin to cure, while pressing the electronic component against the circuit member, and then releasing pressure applied for the pressing; and subjecting the solder interposed between the first and second electrodes to a second heating with the pressure released, and thus melting the solder to electrically connect the first and second electrodes.

A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component. A curing degree curve is created. The curing degree curve indicates, with respect to each of heating temperatures, relationship between heating time and curing degree of the thermosetting resin. On the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin, at a first heating temperature, is calculated. The first heating temperature is one of the heating temperatures.

A solder reflow apparatus may include a vapor generating chamber configured to accommodate a heat transfer fluid, a heater configured to heat the heat transfer fluid, a vertical transfer portion, and at least one substrate stage. The vertical transfer portion may include a vertical conveyer supported by a driving pulley and a driven pulley so as to be rotatable in an endless track, the vertical conveyer having a conveying route of a descending path and an ascending path in the vapor generating chamber, and at least one substrate stage fixedly fastened to one side of the vertical conveyor by a fastening portion so as to be raised and lowered in the vapor generating chamber by rotation of the vertical conveyor. The at least one substrate stage may be configured to support a substrate on which an electronic component may be mounted via a solder.

A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component. A curing degree curve is created. The curing degree curve indicates, with respect to each of heating temperatures, relationship between heating time and curing degree of the thermosetting resin. On the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin, at a first heating temperature, is calculated. The first heating temperature is one of the heating temperatures.

A solder reflow apparatus includes a vapor generating chamber configured to accommodate a heat transfer fluid and to accommodate saturated vapor generated by heating the heat transfer fluid; a heater configured to heat the heat transfer fluid accommodated in the vapor generating chamber; a substrate stage configured to be movable upward and downward within the vapor generating chamber, the substrate stage including a seating surface; vapor passages penetrating the substrate stage and configured to allow the vapor to move therethrough; and suction passages penetrating the substrate stage to be open to the seating surface and in which at least a partial vacuum is generated.

The disclosure provides a light-emitting device and a displayer. Herein, the light-emitting device includes a substrate, a light-emitting chip, a first light-transmitting layer, a second light-transmitting layer and a nano coating. The light transmittance of the second light-transmitting layer is greater than the light transmittance of the first light-transmitting layer. A reference surface corresponding to the light-emitting chip is arranged above the substrate, and the reference surface is higher than the bottom surface of the light-emitting chip and not higher than the top surface of the light-emitting chip. The first light-transmitting layer covers the surface of the light-emitting chip below the reference surface, and the second light-transmitting layer covers the surface of the light-emitting chip above the reference surface. The nano coating covers the outer surface of the first light-transmitting layer, the outer surface of the second light-transmitting layer and the side surface of the substrate.

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

The invention provides a circuit pin positioning structure, a fabrication method of soldered circuit elements and a method of forming circuit pins of a stacked package, applicable to a semiconductor package structure. A positioning rack and a plurality of conductor elements are used. A plurality of positioning holes are provided on a bottom surface of the positioning rack to form a conductor positioning area, and an operational portion is formed on an opposing surface away from the conductor positioning area, for being mounted with pick and place equipment. The conductor elements are positioned in the positioning holes. When the pick and place equipment loads and moves the positioning rack to preformed circuit contacts of the stacked package, the conductor elements are soldered to the preformed circuit contacts and then the positioning rack is removed.